System Introduction1-23Table 1-13 GPIO Port Definition Map IIGPIO I/O DescriptionP2.1 O NCP2.2 (SM5_BAYSW) I Detect FDD/CD bay installed or notP2.3 O NCP2.4 O NCP2.5 O NCP2.6 O NCP2.7 O NCP3.0 (SM5_RXD) I Receiving data from KBC to SMCP3.1 (SM5_TXD) O Transmitting data from SMC to KBCP3.2 (SM5_DOCKSW) I Dock switch senseP3.3 (CF5_DOCKED) I Detect completely docked or notP3.4 (SM5_LIDSW) I Lid switch senseP3.5 (SM5_OVTMP#) O CPU or system over temperatureP3.6 O NCP3.7 (SM5_ON_RES_SW) O ON/RESUME switch for Japan versionP4.0 (SM5_FANON) O Fan controlP4.1 NCP4.2 (SM5_FLOATREQ#) O Docking float requestP4.3 (SM5_UNDOCK_GNT#) O Undock grantP4.4 (SM5_ICONT) I Charge current controlP4.5 (SM5_FLAOTGNT#) I Docking float grantP4.6 (SM5_PWRRDYB) O Power ready, delay about 4ms after power goodP4.7 (SM5_SYSRDY) O NCP5.0 (CHARGSP) I Charging set pointP5.1 (SM5_VBAT_MAIN) I Main battery detectionP5.2 (SM5_ACPWRGD) I AC source power goodP5.3 (SM5_NBPWRGD) I 3V, 5V, processor module power goodP5.4 (SM5_ATFINT) I CPU thermal interrupt (panic)P5.5 (SM5_THERM_SYS) I System thermal input (analog)P5.6 (SM5_ACIN_AUX) I Aux AC adapter inP5.7 (SM5_ACIN_MAIN) I Main AC adapter inPWM1# (SM5_CONT) O LCD contrastPWM0# (SM5_BRIT) O LCD brightness1.6.6 PCI Devices AssignmentTable 1-14 PCI Devices Assignment
