Basler A500k User Manual
Also see for A500k: Wood burning fireplaceUser manual
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Contents
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Basic Operation and FeaturesBasler A500k Series 3-1PRELIMINARY3 Basic Operation and Features3.1 Functional DescriptionBASLER A500k area scan cameras employ a CMOS-sensor chip which provides features such asa full frame shutter, electronic exposure time control and anti-blooming. Exposure time iscontrolled either internally via an internal sync signal (free-run mode) or externally via an externaltrigger (ExSync) signal. The ExSync signal facilitates periodic or non-periodic pixel readout.In any free-run mode, the camera generates its own internal control signal and the internal signalis used to control exposure and charge read out. When operating in free-run, the camera outputsframes continuously.When exposure is controlled by an ExSync signal, exposure time can be either edge-controlled,level-controlled or programmable. In edge-controlled mode, charge is accumulated from the risingedge to the next rising edge of ExSync. The rising edge of ExSync also triggers the readout. Inlevel-controlled mode, charge is accumulated when the ExSync signal is low and a rising edge ofExSync triggers the readout. In programmable mode, exposure time can be programmed to apredetermined time period. In this case, exposure begins on the rising edge of ExSync andaccumulated charges are read out when the programmed exposure time ends.The A504k/kc has a special feature: In addition to sending video data to a framegrabber, it can beoutput to an VGA monitor (640 x 480 pixels). In VGA exposure mode the camera generates itsown internal control signal and the internal signal is used to control exposure and charge read out.The frame frequency is set to 60 Hz. The camera outputs frames continuously to the monitor and,at the same time, to the Camera Link output.At readout, all accumulated charges of all pixels are simultaneously transported from the light-sensitive sensor elements (pixels) to the pixel memory (full frame shutter). There is a pixelmemory for each pixel. As a consequence, the camera can be exposed and read out at the sametime. The charges of the pixel memory are amplified. The pixel memories can be connected to abus. There is one bus for each vertical column. At the end of each bus, there is an analog/digitalconverter (ADC).For readout, the pixel memories can be addressed linewise by closing a switch that connects thepixel memory of the addressed lines to the busses. Before the analog video data enters the ADC,the offset is added, plus a value that corrects column fixed pattern noise. The analog video datais digitized by a ten bit, Analog to Digital converter (ADC). The ADC’s reference value is used toset the gain. The digitized video data then passes a digital 128 stage shift register, which outputs10 x 10 Bit of data in parallel with each cycle. Then the 10 Bit data enters the digital shifter in theFPGA, which selects the 8 bits out of the 10 bits output by the sensor. The next step of the dataflow is different in the A504k/kc and the A501k/kc:• In the A504k/kc, the data is formatted to be output in 10 data streams in parallel (10 taps). |
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