Caen V1724 Series Technical Information Manual
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P R E L I M I N A R YDocument type: Title: Revision date: Revision:User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 7NPO: Filename: Number of pages: Page:00103/05:V1724x.MUTx/07 V1724_REV7.DOC 63 223.3.3. Sample modeIn Sample mode only the first value sampled after the S-IN signal leading edge is stored;; data storage takes place by couples of samples (two 32 bit long words) per time. Forthis purpose it is necessary to:− Set bits [1:0] of Acquisition Control register to S-IN GATE MODE− Set bit [0] of Channel Configuration Register (see § 4.12) to 1Note that, if the S-IN signal is not synchronised with the sampling clock, then a 1 clockperiod jitter occurs between the S-IN leading edge and the actual sampling time.D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10SAMPLING CLOCKS-INADC DATAS0S4S 8 S12S16S20 S24S28S 32S36S40D11 D12S44S48S52D1 D1 D1 D1 D1D5D1D5D1D5D1D5D1D5D9D1D5D9D1D5D9MEMORYBUFFERD1D5D9Fig. 3.6: Data storage2 in Sample Mode3.3.4. Acquisition Triggering: Samples and EventsWhen the acquisition is running, a trigger signal allows to:− store a Trigger Time Tag (TTT): the value of a 32 bit counter which steps on withthe sampling clock and represents a time reference− increment the EVENT COUNTER (see § 4.29)− fill the active buffer with the pre/post-trigger samples, whose number isprogrammable via Post Trigger Setting register (see § 4.23); the Acquisition windowwidth is determined via Buffer Organization register setting (see § 4.15,); then thebuffer is frozen for readout purposes, while acquisition continues on another buffer.Table 3.1: Buffer OrganizationSIZE of one BUFFER (samples)REGISTER(see § 4.15)BUFFER NUMBERSRAM 1MB/ch (512KS) SRAM 8MB/ch (4MS)0x00 1 512K 4M0x01 2 256K 2M0x02 4 128K 1M0x03 8 64K 512K0x04 16 32K 256K0x05 32 16K 128K0x06 64 8K 64K0x07 128 4K 32K0x08 256 2K 16K0x09 512 1K 8K0x0A 1024 512 4K2 Underscored = stored |
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