Caen V1724 Series Technical Information Manual
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Document type: Title: Revision date: Revision:User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 7NPO: Filename: Number of pages: Page:00103/05:V1724x.MUTx/07 V1724_REV7.DOC 63 56Bit Function[0] 0 = TRG/CLK are NIM I/O Levels1 = TRG/CLK are TTL I/O Levels4.26. Channel Enable Mask (0x8120; r/w)Bit Function[7] 0 = Channel 7 disabled1 = Channel 7 enabled[6] 0 = Channel 6 disabled1 = Channel 6 enabled[5] 0 = Channel 5 disabled1 = Channel 5 enabled[4] 0 = Channel 4 disabled1 = Channel 4 enabled[3] 0 = Channel 3 disabled1 = Channel 3 enabled[2] 0 = Channel 2 disabled1 = Channel 2 enabled[1] 0 = Channel 1 disabled1 = Channel 1 enabled[0] 0 = Channel 0 disabled1 = Channel 0 enabledEnabled channels provide the samples which are stored into the events (and not erased).The mask cannot be changed while acquisition is running.4.27. ROC FPGA Firmware Revision (0x8124; r)Bit Function[31:16] Revision date in Y/M/DD format[15:8] Firmware Revision (X)[7:0] Firmware Revision (Y)Bits [31:16] contain the Revision date in Y/M/DD format.Bits [15:0] contain the firmware revision number coded on 16 bit (X.Y format).4.28. Downsample Factor (0x8128; r/w)Bit Function[31:0]This register allows to set N: sampling frequency will be divided byN+1.Downsampling is enabled via Acquisition Control register; see § 4.174.29. Event Stored (0x812C; r)Bit Function[31:0] This register contains the number of events currently stored in theOutput BufferThis register value cannot exceed the maximum number of available buffers according tosetting of buffer size register. |
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