Dell External OEMR R910 Technical Manual

Also see for PowerEdge R910: Manual Update Update Hardware owner's manual Update

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Dell External OEMR R910 Technical Manual Manual pdf 41 page image

DellDell PowerEdge R910 Technical Guide 419 ChipsetThe R910 system-board incorporates the Intel 7500 chipset (Boxboro‐EX) for I/O and processorinterfacing. The Intel 7500 chipset is designed to support Intel’s 6500 and 7500 4S processor family,QPI interconnect, DDR3 memory technology, and PCI Express Generation 2. The Intel 7500 chipsetconsists of the EX IOH, Intel® 7500 Scalable Memory Buffer, and the ICH10 South Bridge.9.1 Intel 7500 Chipset I/O Hub (IOH)The R910 motherboard incorporates dual Intel 7500 chipset IOH to provide a link between the IntelXeon 6500 and 7500 series 4S processors and the I/O components. The main components of the IOHconsist of two full-width QPI links (one to each processor), 72 lanes of PCIe Gen2, and a x4 DMI linkto connect directly to the ICH10 South Bridge.9.2 IOH QuickPath Interconnect (QPI)The QuickPath Architecture consists of serial point-to-point interconnects for the processors and theIOH. The PowerEdge R910 has a total of four QuickPath Interconnect (QPI) links including one linkconnecting the processors and links connecting both processors with the IOH and links connectingboth IOHs. Each link consists of 20 lanes (full-width) in each direction with a link speed of 6.4 GT/s.An additional lane is reserved for a forwarded clock. Data is sent over the QPI links as packets.The QuickPath Architecture features four layers. The Physical layer consists of the actual connectionbetween components. It supports Polarity Inversion and Lane Reversal for optimizing componentplacement and routing. The Link layer is responsible for flow control and the reliable transmission ofdata. The Routing layer is responsible for the routing of QPI data packets. Finally, the Protocol layeris responsible for high-level protocol communications, including the implementation of a MESIF(Modify, Exclusive, Shared, Invalid, Forward) cache coherence protocol.9.3 PCI EXPRESS GENERATION 2PCI Express is a serial point to point interconnects for I/O devices. PCIe Gen2 doubles the signalingbit rate of each lane from 2.5 Gb/s to 5 Gb/s. Each of the PCIe Gen2 ports is backwards compatiblewith Gen1 transfer rates.9.4 Direct Media Interface (DMI)The DMI (previously called the Enterprise Southbridge Interface) connects the Boxboro‐EX Legacy IOHwith the Intel I/O Controller Hub (ICH). The DMI is equivalent to a x4 PCIe Gen1 link with a transferrate of 1 GB/s in each direction.9.5 Intel I/O Controller Hub 10 (ICH10)ICH10 is a highly integrated I/O controller, supporting the following functions:• Six x1 PCIe Gen1 ports, with the capability of combining ports 1-4 as a x4 link• These ports are used on PowerEdge R910 for slot 5• PCI Bus 32-bit Interface Rev 2.3 running at 33 MHz• Up to six Serial ATA (SATA) ports with transfer rates up to 300 MB/s• R910 features one SATA port for optional internal optical drive• Six UHCI and two EHCI (High-Speed 2.0) USB host controllers, with up to twelve USB ports(R910 has four external USB ports and one internal ports dedicated for IDSM and embeddedstorage)• Power management interface (ACPI 3.0b compliant)