Dell POWEREDGE R610 Technical Manualbook

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Dell POWEREDGE R610 Technical Manualbook Manual pdf 30 page image

Dell™ PowerEdge™ R610 Technical Guidebook30h. Optimizer (independent channel) modeIn this mode, all three channels are populated with identical memory modules. This mode permits alarger total memory capacity but does not support SDDC with x8-based memory modules.A minimal single-channel configuration of 1GB memory modules per processor is also supported inthis mode.sectiOn 8. chiPseta. Overview / DescriptionThe PowerEdge R610 planar incorporated the Intel 5520 chipset (code named Tylersburg) for I/O andprocessor interfacing. Tylersburg is designed to support Intel's 5500 series processors (code namedNehalem-EP), QPI interconnect, DDR3 memory technology, and PCI Express Generation 2. TheTylersburg chipset consists of the Tylersburg-36D IOH and ICH9.The Intel 5520 chipset (code named Tylersburg) I/O Hub (IOH)The planar uses the The Intel® 5520 chipset (code named Tylersburg) I/O Hub (IOH)-36D IOH to providea link between the 5500 series 2S processor (Nehalem EP) and I/O components. The main componentsof the IOH consist of two full-width QuickPath Interconnect links (one to each processor), 36 lanes ofPCI Express Gen2, a x4 Direct Media Interface (DMI), and an integrated IOxAPIC.IOH QuickPath Interconnect (QPI)The QuickPath Architecture consists of serial point-to-point interconnects for the processors and theIOH. The PowerEdge R610 has a total of three QuickPath Interconnect (QPI) links: one link connectingthe processors and links connecting both processors with the IOH. Each link consists of 20 lanes(full-width) in each direction with a link speed of up to 6.4 GT/s. An additional lane is reserved for aforwarded clock. Data is sent over the QPI links as packets.The QuickPath Architecture implemented in the IOH and CPUs features four layers. The Physical layerconsists of the actual connection between components. It supports Polarity Inversion and Lane Reversalfor optimizing component placement and routing. The Link layer is responsible for flow control and thereliable transmission of data. The Routing layer is responsible for the routing of QPI data packets. Finally,the Protocol layer is responsible for high-level protocol communications, including the implementation ofa MESIF (Modify, Exclusive, Shared, Invalid, Forward) cache coherence protocol.