Dell PowerEdge R210 II Technical Manual

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Dell PowerEdge R210 II Technical Manual Manual pdf 28 page image

Dell28PowerEdge R210 II Technical Guide8 Chipset8.1 OverviewThe PowerEdge R210 II planar incorporates the Intel C200 Series PCH chipset. The features listedbelow are part of the chipset.8.2 Direct Media InterfaceDirect Media Interface (DMI) is the chip-to-chip connection between the processor and C200 serieschipset. This high-speed interface integrates advanced priority-based servicing allowing forconcurrent traffic and true isochronous transfer capabilities. Base functionality is completelysoftware-transparent, permitting current and legacy software to operate normally.8.3 PCI Express InterfaceThe C200 series provides up to 8 PCI Express root ports. Each root port supports 5GT/s bandwidth.PCI Express Root Ports 1-4 can be statically configured as four x1 ports or ganged together to formone x4 port. Ports 5 and 6 can only be used as two x1 ports.8.4 SATA InterfaceThe chipset has two integrated SATA host controllers that support independent DMA operation on upto six port: 6 x 3Gb/s SATA. The SATA controller contains two modes of operation, a legacy modeusing I/O space and an AHCI mode using memory space. Software that uses legacy mode will not haveAHCI capabilities.8.5 AHCIThe chipset provides hardware support for Advanced Host Controller Interface (AHCI), a newprogramming interface for SATA host controllers. Platforms supporting AHCI may take advantage ofperformance features such as no master/slave designation for SATA devices—each device is treatedas a master—and hardware-assisted native command queuing. AHCI also provides usabilityenhancements such as Hot-Plug. AHCI requires appropriate software support (for example, an AHCIdriver) and for some features, hardware support in the SATA device or additional platform hardware.8.6 PCI InterfaceThe C200 Series chipset PCI interface provides a 33 MHz, Revision 2.3 implementation. The chipsetintegrates a PCI arbiter that supports up to four external PCI bus masters in addition to the internalrequests. This allows for combinations of up to 8 PCI down devices and PCI slots.8.7 Low Pin Count (LPC) InterfaceThe LPC bridge function of the PCH resides in PCI Device 31: Function 0. In addition to the LPC bridgefunction, D31:F0 contains other functional units including DMA, Interrupt controllers, Timers, PowerManagement, System Management, GPIO, and RTC.8.8 Serial Peripheral Interface (SPI)The chipset implements an SPI Interface as an alternative interface for the BIOS flash device. An SPIflash device can be used as a replacement for the FWH, and is required to support Gigabit Ethernet,