Dell PowerEdge R210 II Technical Manual

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Dell29PowerEdge R210 II Technical GuideIntel® Active Management Technology, and integrated Intel Quiet System Technology. The chipsetsupports up to two SPI flash devices with speed up to 20 MHz, 33 MHz utilizing two chip select pins.8.9 Compatibility ModuleThe DMA controller incorporates the logic of two 82C37 DMA controllers, with seven independentlyprogrammable channels. Channels 0–3 are hardwired to 8-bit, count-by-byte transfers, and channels5–7 are hardwired to 16-bit, count-by-word transfers. Any two of the seven DMA channels can beprogrammed to support fast Type-F transfers. Channel 4 is reserved as a generic bus master request.The chipset supports LPC DMA, which is similar to ISA DMA, through the DMA controller. LPC DMA ishandled through the use of the LDRQ# lines from peripherals and special encoding on LAD[3:0] fromthe host. Single, Demand, Verify, and Increment modes are supported on the LPC interface.The timer/counter block contains three counters that are equivalent in function to those found inone 82C54 programmable interval timer. These three counters are combined to provide the systemtimer function, and speaker tone. The 14.31818 MHz oscillator input provides the clock source forthese three counters.The chipset provides an ISA-Compatible Programmable Interrupt Controller (PIC) that incorporatesthe functionality of two, 82C59 interrupt controllers. The two interrupt controllers are cascaded sothat 14 external and two internal interrupts are possible. In addition, the chipset supports a serialinterrupt scheme.All of the registers in these modules can be read and restored. This is required to save and restoresystem state after power has been removed and restored to the platform.8.10 Advanced Programmable Interrupt Controller (APIC)In addition to the standard ISA compatible Programmable Interrupt Controller (PIC) described in theprevious section, the Ibex Peak incorporates the Advanced Programmable Interrupt Controller (APIC).8.11 USB InterfaceThe C200 Series chipset contains up to two Enhanced Host Controller Interface (EHCI) host controllersthat support USB high-speed signaling. High-speed USB 2.0 allows data transfers up to 480 Mb/swhich is 40 times faster than full-speed USB. The chipset also contains up to seven Universal HostController Interface (UHCI) controllers that support USB full-speed and low-speed signaling.The chipset supports up to fourteen USB 2.0 ports. All fourteen ports are high-speed, full-speed, andlow-speed capable. The port-routing logic determines whether a USB port is controlled by one of theUHCI or EHCI controllers.8.12 Real-Time Clock (RTC)The Real Time Clock (RTC) module provides a battery backed-up date and time keeping device withtwo banks of static RAM with 128 bytes each, although the first bank has 114 bytes for generalpurpose usage. Three interrupt features are available: time of day alarm with once a second to oncea month range, periodic rates of 122 μs to 500 ms, and end of update cycle notification. Seconds,minutes, hours, days, day of week, month, and year are counted. Daylight savings compensation is nolonger supported. The hour is represented in twelve or twenty-four hour format, and data can berepresented in BCD or binary format. The design is functionally compatible with the MotorolaMS146818B. The time keeping comes from a 32.768 kHz oscillating source, which is divided toachieve an update every second. The lower 14 bytes on the lower RAM block has very specific