Denon DVD-5900 Service Manual

Also see for DVD-A11: Operating instructions Operating instructions

Contents

Denon DVD-5900 Service Manual Manual pdf 66 page image

6666DVD-5900/DVD-A11K4S643232E (MA: IC701,VI: IC733)VDDDQ0V DDQDQ1DQ2V SSQDQ3DQ4V DDQDQ5DQ6V SSQDQ7N.CVDDDQM0WECASRASCSN.CBA0BA1A10/APA0A1A2DQM2VDDN.CDQ16V SSQDQ17DQ18V DDQDQ19DQ20V SSQDQ21DQ22V DDQDQ23VDD1234567891011121314151617181920212223242526272829303132333435363738394041424386858483828180797877767574737271706968676665646362616059585756555453525150494847464544VSSDQ15VSSQDQ14DQ13VDDQDQ12DQ11VSSQDQ10DQ9VDDQDQ8N.CVSSDQM1N.CN.CCLKCKEA9A8A7A6A5A4A3DQM3VSSN.CDQ31VDDQDQ30DQ29VSSQDQ28DQ27VDDQDQ26DQ25VSSQDQ24VSSPIN CONFIGURATION BLOCK DIAGRAMBank SelectData Input Register512K x 32512K x 32Sense AMPOutput BufferI/O ControlColumn DecoderLatency & Burst LengthProgramming RegisterAddress RegisterRow BufferRefresh CounterRow Decoder Col. BufferLRASLCBRLCKELRAS LCBR LWE LDQMCLK CKE CS RAS CAS WE DQMLWELDQMDQiCLKADDLCAS LWCBR512K x 32512K x 32Timing RegisterPIN FUNCTION DESCRIPTIONPin Name Input FunctionCLK System clock Active on the positive going edge to sample all inputs.CS Chip select Disables or enables device operation by masking or enabling all inputs exceptCLK, CKE and DQM.CKE Clock enableMasks system clock to freeze operation from the next clock cycle.CKE should be enabled at least one cycle prior to new command.Disables input buffers for power down mode.A 0 ~ A10 Address Row/column addresses are multiplexed on the same pins.Row address : RA 0 ~ RA 10 , Column address : CA 0 ~ CA 7BA0,1 Bank select address Selects bank to be activated during row address latch time.Selects bank for read/write during column address latch time.RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low.Enables row access & precharge.CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low.Enables column access.WE Write enable Enables write operation and row precharge.Latches data in starting from CAS, WE active.DQM0 ~ 3 Data input/output mask Makes data output Hi-Z, t SHZ after the clock and masks the output.Blocks data input when DQM active.DQ 0 ~ 31 Data input/output Data inputs/outputs are multiplexed on the same pins.V DD /V SS Power supply/ground Power and ground for the input buffers and the core logic.V DDQ /V SSQ Data output power/ground Isolated power supply and ground for the output buffers to provide improved noiseimmunity.NC No Connection This pin is recommended to be left No connection on the device.www. xiaoyu163. comQQ 376315150 992894298TEL 13942296513 992894298051513673QQTEL 13942296513 QQ 376315150 892498299TEL 13942296513 QQ 376315150 892498299http://www.xiaoyu163.comhttp://www.xiaoyu163.com