Echelon LONWORKS PLT-22 User Manual
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Contents
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EMI Design IssuesThe high-speed digital signals associated with microcontroller designs can generateunintentional electromagnetic interference (EMI). High-speed voltage transitionsgenerate RF currents that can radiate from a product if a nearby length of wire orpiece of metal acts as an antenna.Products that use a PLT-22 transceiver together with a Neuron Chip will generallyneed to demonstrate compliance with EMI limits enforced by various regulatoryagencies. In the USA, the FCC6 requires that unintentional radiators comply withPart 15 level “A” for industrial products, and level “B” for consumer and householdproducts. Most European countries require compliance to CENELEC EN 50065-1.Similar regulations are imposed in most countries throughout the world.In addition to the following discussion, designers of PLT-22 transceiver-based nodesare strongly encouraged to read reference [11] for a good treatment of EMC. TheEDN Designer's Guide to EMC12 is also a good source of design advice regardingEMC issues.Designing Systems for EMC (Electromagnetic Compatibility)Careful PCB layout is important to ensure that a PLT-22 transceiver-based node willachieve the desired level of EMC. A typical PLT-22 transceiver-based node will haveseveral digital signals switching in the 1MHz-10MHz range. These signals willgenerate both voltage noise near the signal traces, and current noise in the signaland power supply traces. The goal of good node design is to keep voltage and currentnoise from coupling out of the product enclosure.It is very important to minimize the “leakage” capacitance from circuit traces in thenode to any external metal near the node because this capacitance provides a pathfor the digital noise to couple out of the product enclosure. Figure 6.1 shows theleakage capacitances to earth ground from a node's logic ground (C leak,GND ) andfrom a digital signal line in the node (C leak,SIGNAL). If the PLT-22 transceiver-based node is housed inside a metal chassis, then that metal chassis will probablyhave the largest leakage capacitance to other nearby pieces of metal. If the node ishoused inside a plastic package, then PCB ground guarding must be used tominimize C leak,SIGNAL. Effective guarding of digital traces with logic groundreduces C leak,SIGNAL significantly, which in turn reduces the level of common-modeRF currents driven onto the AC mains.When a node is mounted near a piece of metal, especially metal that is earthgrounded, any leakage capacitance from fast signal lines to that metal will provide apath for RF currents to flow. When V gate is pulled down to logic ground, the voltageof logic ground with respect to earth ground will increase slightly. When V gate pullsup to V DD5, logic ground will be pushed down slightly with respect to earth ground.As C leak,SIGNAL increases, a larger current flows during V gate transitions,generating more common-mode RF current. This common-mode RF current cangenerate EMI in the 30MHz-300MHz frequency band, thereby exceedingFCC/CENELEC levels, even when C leak,SIGNAL from a clock line to earth ground isless than 1pF. This means that it is essential to guard the clock lines.6-2 Design and Test for Electromagnetic Compatibility |
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