GE Multilin B30 Bus Differential System 5-1195 SETTINGS 5.5 FLEXLOGIC55.5.3 FLEXLOGIC EVALUATIONEach equation is evaluated in the ascending order in which the parameters have been entered.FlexLogic provides built-in latches that by definition have a memory action, remaining in the set state after the setinput has been asserted. These built-in latches are reset dominant, meaning that if logical "1" is applied to both setand reset entries simultaneously, then the output of the latch is logical "0." However, they are volatile, meaning thatthey reset upon removal of control power.When making changes to FlexLogic entries in the settings, all FlexLogic equations are re-compiled whenever anynew FlexLogic entry value is entered, and as a result of the re-compile all latches are reset automatically.5.5.4 FLEXLOGIC EXAMPLEThis section provides an example of implementing logic for a typical application. The sequence of the steps is quite impor-tant as it should minimize the work necessary to develop the relay settings. Note that the example presented in the figurebelow is intended to demonstrate the procedure, not to solve a specific application situation.In the example below, it is assumed that logic has already been programmed to produce virtual outputs 1 and 2, and is onlya part of the full set of equations used. When using FlexLogic, it is important to make a note of each virtual output used – avirtual output designation (1 to 96) can only be properly assigned once.Figure 5–40: EXAMPLE LOGIC SCHEME1. Inspect the example logic diagram to determine if the required logic can be implemented with the FlexLogic operators.If this is not possible, the logic must be altered until this condition is satisfied. Once this is done, count the inputs toeach gate to verify that the number of inputs does not exceed the FlexLogic limits, which is unlikely but possible. If thenumber of inputs is too high, subdivide the inputs into multiple gates to produce an equivalent. For example, if 25inputs to an AND gate are required, connect Inputs 1 through 16 to AND(16), 17 through 25 to AND(9), and the outputsfrom these two gates to AND(2).Inspect each operator between the initial operands and final virtual outputs to determine if the output from the operatoris used as an input to more than one following operator. If so, the operator output must be assigned as a virtual output.For the example shown above, the output of the AND gate is used as an input to both OR#1 and Timer 1, and musttherefore be made a virtual output and assigned the next available number (i.e. Virtual Output 3). The final output mustalso be assigned to a virtual output as virtual output 4, which will be programmed in the contact output section to oper-ate relay H1 (that is, contact output H1).NOTELATCHCONTACT INPUT H1cState=ClosedXORANDResetSetVIRTUAL OUTPUT 2State=ONVIRTUAL INPUT 1State=ONDIGITAL ELEMENT 1State=PickupDIGITAL ELEMENT 2State=OperatedOR #2 Operate OutputRelay H1OR #1(800 ms)Timer 1Time Delayon Pickup(200 ms)Timer 2Time Delayon DropoutVIRTUAL OUTPUT 1State=ON827025A2.vsd
