Harris Platinum HT EL 2000LS Technical Manual

Harris Platinum HT EL 2000LS Technical Manual Manual pdf 40 page image

sample selected and the decimal point selection for the digitaldisplay. The enable line (EN_SQ, EN_VOLT, EN_CUR) to themultiplexers is asserted HI and the decimal points (DP1*, DP2*,DP3*) are asserted low to turn on the display decimal point.NOTE: The (*) character is used to denote a signal is assertedLOW when true.Table 4-1 shows the address of A0, A1, & A3 (ADR) the threebit meter selection counter coupled to the functions displayed.4.3.5 Loss Of Video Delay DetectorThe Loss of Video Delay Detector, page two, is made up of U8through U14 to form a function “on” video present delay of 3.5to 9.2 seconds and on video loss a delay of 1 to 2.7 minutes. Thefunction can be inhibited by placing JP1 in the 2-3 position orenabled in the 1-2 position.With JP1 in the NORMAL (1-2) position and video present thereset to U11-6 is asserted low allowing the oscillator in U11 torun starting a terminal count of 32768. This will assert U11-8 Hiwhich clocks U13-3 (D latch) Hi causing U13-5 to change to thestate of the D input which is Hi. This will assert U13-6 lowcausing U14-1 to assert Hi signaling the delayed presence ofvideo and un-mute the rf mute circuit.On the loss of video U11-6 is asserted Hi resetting the videopresent counter and U12-6 is asserted low allowing U12 to startcounting. At the time between loss of video and the terminalcount of U12 the visual rf level is reduced by asserting U16-18low which inserts R41 CW LEVEL SET pot in the visual powercontrol circuit. At the terminal count of 32768 U12-8 will assertHi causing U14-10 to assert low causing U13-1 to reset the Dlatch asserting U13-6 Hi causing U14-1 low signaling the de-layed loss of video which will rf mute exciter output.4.3.6 Override/Normal SelectionLocated in the upper right hand corner of the meter board is JP1NORMAL/OVERRIDE jumper selection. In the NORMAL po-sition the delay timers operate as outlined above. In the OVER-RIDE position both delay timers are inhibited and the loss ofvideo signal is passed through U14 to rf mute circuit of theexciter.4.3.7 Clock CircuitsSheet 4 of the schematic shows the clock PALs for the up/downcounters for VISUAL RAISE/LOWER U18, AURALRAISE/LOWER U19, METER CLOCK U20, and METER SE-LECT U17. U18 and U19 are clocked by the 300Hz oscillatorU22 to generate the VIS_PWR_CLK and the AUR_PWR_CLKsignals to drive the visual and aural up/down 12 bit counters.Upon pressing an UP or DOWN button, U18 or U19 pin 23PWR_CLK will issue one pulse then wait for 2 seconds and startissuing a 300Hz clock rate if the button is still pressed.IC U18 also generates a 9.5Hz clock used by the METERCLOCK GATE U20 which operates similar to U18 & U19 butat a slower one pulse per 1.17 second rate to clock U17 METERSELECT 4 bit counter.Oscillator U22 is running about 77.6kHz and is programmed fora divide by 256 to produce the 300Hz output frequency.4.3.8 BATTERY (BAT) SUPPLY VOLTAGEAll the PALs operate from the BAT Vcc supply line whichmaintains voltage on the counters in the event of a power failure.At some point after that all counters will be reset to 0 on powerreturn if BAT drops to a low enough voltage. BAT is supplied bythree AA size batteries mounted on the rear of the exciter.4.3.9 Visual Power ControlThe visual power control is shown on sheet 5 of the schematicand controls the rf output of the visual channel. The 12 bitup/down counter consists of U26 & U27 which supplies a binarycode to the DAC U25 which controls the gain of U24-1VIS_DAC_BUF. The signal is passed through the rf mute switchU23-1 to 2 and on to U23-3 to 4 CW LEVEL SET switch and onto U24-5 VIS_CTRL_BUF subtractor circuit where the visualreflected power foldback input reduces the output when applied.VIS_PWR_CTRL J1-23 will normally swing between 0 and 4volts for a 0 to 1 watt output level but can vary somewhat andwill depend on where R48 VIS_PWR_LIMIT is set.4.3.10 Aural Power ControlThe aural power control shown on sheet 6 of the schematic worksthe same as the visual except there is no CW_LEVEL_SETswitch in the aural path.4.3.11 Power Up ResetThe power up reset circuit is U31 which forms a voltage compa-rator referenced to the 1.23 volts of CR11, normal power faildetection point is about 4.6 volts. When the voltage of U31-3 ismore than U31-2 then U31-1 will assert a Hi removing the powerup reset signal.4.3.12 JP2 & JP3These two jumpers extend AUR_GROUP_DELAY andNOTCH_DIP_ENABLE signals to the remote control interface.4.3.13 FREQ UNLOCKThe unlocked status of the three phased locked oscillator isdisplayed by DS27, DS28, & DS29 and passed to PAL U17where they are combined to produce the signal FREQ_LOCK*on U17-23. FREQ_LOCK* drives the FREQ UNLOCK statusindicator and the U27-11 where it is combined withVIDEO_LOSS_DELAY* to generate RF_MUTE U27-22. Alsoif any FREQ UNLOCK or VIDEO LOSS DELAY is asserted lowthe exciter will mute the rf output.Platinum™ Series4-2 888-2457-001 Rev. B: 7/15/02WARNING: Disconnect primary power prior to servicing.