146Chapter 5 The Power On SequenceThe Power On SequenceThis section describes the normal sequence of events from the time thepower switch is set to 1 until READY (or NOT READY, if so configured by theuser) appears on the LCD.Use this sequence as a reference baseline to help you isolate problems thatoccur before the printer completes its boot and initialization routines.The power on sequence consists of two sets of routines:1. CMX controller board handshake sequences (DC hardware initialization)2. DC software initialization and power upThe routines are listed below, in order of occurrence.CMX Controller Board Handshake SequencesThe first power-up routines are the handshaking sequences which sampleand test the condition of the CMX controller board. The sequences occur asfollows:• Processor Alive — The green LED marked CR1 on the CMX controllerboard is turned on to indicate that the processor received a valid resetvector and the first instructions to the processor are correct. This LED isused to report all DC errors and states.• Test VX Data Bus — A walking zero and one test verifies that all 32 datalines from the VX bus to the processor are connected. If a bad line isdetected, a 4-1-1-XX blink code is sent to the LED on the CMX controller,where XX is the data line plus 1. (For example, a bad data line 8 wouldblink as 4-1-1-9.)• Initialize VX ASIC — The boot code detects the processor type and setsup the internal registers of the VX ASIC.• Initialize Debug Serial Port — The boot code checks the validity of thedebug serial parameters in NVRAM; if they are valid, it sets the baud rate,data type, and which messages should be sent out the debug port. If thevalues in NVRAM are not valid, boot code initializes NVRAM to 9600baud, 8 data bits, one stop, bit, no parity bit, and standard messages.• Turn On Instruction Cache — The instruction cache is turned on to helpspeed up memory tests and the entire boot process.• Enable DRAM Controller — A DRAM controller is built into the VX ASIC.DRAM must be refreshed a few times to operate correctly. To speed theboot process, the refresh rate is temporarily increased. The message“TESTING HARDWARE PLEASE WAIT” is sent to the LCD, during whichtime the refreshes run and finish. At this point, the fans start. Aftersending the message, the refresh rate is set to the proper rate and DRAMis ready to be tested.• Test I/O Clock — The VX ASIC has two clocks for internal timing, aprocessor clock and an I/O clock. The processor clock cannot be checkedbecause the processor will not run without it, but the I/O clock can bechecked. The I/O clock is used for sending data to the operator panel andto get the time for DRAM refreshes. If the boot code detects a problem
