17TK-480/481CIRCUIT DESCRIPTIONFig. 8 PLL block diagram6. Control CircuitThe control circuit consists of microprocessor (IC15) andits peripheral circuits. It controls the TX-RX unit and trans-fers data to and from the display unit. IC15 mainly performsthe following;1) Switching between transmission and reception by PTTsignal input.2) Reading system, group, frequency, and program datafrom the memory circuit.3) Sending frequency program data to the PLL.4) Controlling squelch on/off by the DC voltage from thesquelch circuit.5) Controlling the audio mute circuit by decode data in-put.6) Transmitting tone and encode data.6-1. Memory circuitMemory circuit consists of the CPU (IC15) and a flashmemory (IC17), a flash memory has a capacity of 2M bitsthat contains the transceiver control program for the CPUand data such as transceiver channels and operating fea-tures.This program can be easily written from an external de-vices. The data, such as operating status, is programmedinto the EEPROM (IC16).• Flash MemoryNote : The flash memory holds data such as written withthe FPU (KPG-49D), firmware program (User mode, Testmode, Tuning mode, etc.) This data must be rewritten whenreplacing the flash memory.• EEPROMNote : The EEPROM stores tuning data (Deviation, Squelch,etc.).Realign the transceiver after replacing the EEPROM.VCOIC14 Q10BUFFQ17BUFFD4SWD5SWQ8LPFPLLIC11CVBUFFVCXO MB IC1FCBALDT,CP,EPULCPUIC15TodriveampTo mixerTATA(TA : Low)1858 Fig. 9 Memory circuitCPUFLASHIC15IC17EEPROMIC165. Frequency Synthesizer Unit5-1. Frequency synthesizerThe frequency synthesizer consists of the VCXO (X2),VCO (IC14), PLL IC (IC11) and buffer amplifiers.The VCXO generates 16.8MHz. The frequency stability is1.5ppm within the temperature range of –30 to +60°C. Thefrequency tuning and modulation of the VCXO are done toapply a voltage to pin 1 of the VCXO. The output of theVCXO is applied to pin 8 of the PLL IC.The TK-480’s VCO covers a dual range of the 806~825MHz, and the 851~870MHz. The VCO generates806.15~825.15MHz for providing to the first local signal inreceive. In TA mode, the pin 1 of the VCO goes low and theVCO generates 851~870MHz.The TK-481’s VCO covers a dual range of the 896~902MHz, and the 935~941MHz. The VCO generates890.15~896.15MHz for providing to the first local signal inreceive. In TA mode, the pin 1 of the VCO goes low and theVCO generates 935~941MHz.The output of the VCO is amplified by the buffer amplifier(Q8) and routed to the pin 5 of the PLL IC. Also the output ofthe VCO is amplified by the two-buffer amplifier (Q10, Q17)and routed to the next stage according to T/R switch (D4,D5).The PLL IC consists of a prescaler, fractional divider, ref-erence divider, phase comparator, charge pump. This PLLIC is fractional-N type synthesizer and performs in the100kHz reference signal which is eighth of the channel step(12.5kHz). The input signal from the pins 1 and 5 of the PLLIC is divided down to the 100kHz and compared at phasecomparator. The pulsed output signal of the phase com-parator is applied to the charge pump and transformed intoDC signal in the loop filter (LPF). The DC signal is applied tothe pin 3 of the VCO and locked to keep the VCO frequencyconstant.PLL data is output from DT (pin 52), CP (pin 64) and EP(pin 69) of the microprocessor (IC15). The data are input tothe PLL IC when the channel is changed or when transmis-sion is changed to reception and vice versa. A PLL lock con-dition is always monitored by the pin 21 (UL) of the micro-processor. When the PLL is unlocked, the UL goes low.