Kenwood NXR-800 Service Manual

Also see for NEXEDGE NXR-800: Brochure Instruction manual Instruction manual Instruction manual Instruction manual

Contents

NXR-800174-7. Receiver PLL circuitsThe receiver unit (X55-310) has the 1st-PLL circuit forcontrolling the VCO that generates the hetero signal to thefirst local oscillator, and the 2nd-PLL circuit for controllingthe VCO that generates the hetero signal to the second localoscillator.The 1st-PLL circuit consists of the VCO (Q7 and Q8),the Buffer amplifier (Q17), the RF amplifi ers (Q16 and Q3),the PLL-IC (IC5), the Active loop fi lters (Q2 and Q4) and theBand switches (Q14, Q10, Q11 and Q59). The signal in the318.05~334.00MHz band generated by VCO Q7 and the334.05~350.05MHz band generated by VCO Q8 is input toIC5 (pin5) via Q17 and Q16 as the Fin signal. The 6MHzreference signal generated by the DDS-IC (IC7) is input toIC5 (pin8) via Q3. Two signals, Fin and REFin, are phase-compared as the 100kHz comparison frequency by eachfrequency divider. The VCO output with the frequency syn-chronized is input to the 1st-Mixer as the fi rst local oscillatorLower hetero signal approximately +17dBm via Q17, Q23,and Q18. The control voltage is input to IC30 (ADC) pin16via IC6.Meanwhile, the 2nd-PLL circuit consists of the VCO (Q24),the Buffer amplifier (Q33), the RF amplifier (Q38, Q22),and the PLL-IC (IC11). The 99.0MHz signal generated byQ24 is input to IC11 (pin5) as the Fin signal via Q38. The19.2MHz Internal reference clock distributed by the transmit-ter unit (X56-312) is input as the REFin signal to IC11 (pin8)via Q22. Two signals, Fin and REFin, are phase-comparedby each frequency divider as the comparison frequency of200kHz. The VCO output with the frequency synchronizedis input to IC9 (prescaler IC) pin2 via Q33 and Q21. The49.5MHz signal is frequency-divided into halves by IC9 andis excited by Q53 and distributed. One is input to IC12 (pin1)via Buffer amplifier_Q35. The other is input to IC13 (pin4)via Buffer amplifier_Q36. Both are input as approximately–16dBm for the second local oscillator Lower hetero signal.The control voltage at this point is input to IC30 (ADC) pin10via IC33.4-8. AVR circuitThe power supply voltage supplied from the power unit(X45-382 C/5) is distributed from the receiver unit (X55-310)CN44 to IC24 (8V), IC25 (8V), IC26 (9V), and IC27 (9V) viathe Q52 DC switch. The output of IC24 is supplied to the1st-IF circuits, the 1st-Local amplifiers and the IF system IC_IC12 via IC15 (5V). Further, the output of IC25 is distributedto IC16 (5V), IC17 (5V), IC18 (5V) and IC19 (5V). The out-put of IC16 is supplied to IF system IC_IC13. The output ofIC17 is supplied to the 2nd-Local amplifiers. The output ofIC18 is supplied to the 1st-PLL and the 2nd-PLL. The outputof IC19 is supplied to the DDS circuit. The output of IC26 issupplied to LNA_Q1. The output of IC27 is supplied to theVCO buffer amplifi ers_Q17, Q33, the 1st-VCO and the 2nd-VCO via Active ripple fi lters_Q9, Q27, and to the Active loopfi lter_Q2, Q4 via the Active ripple fi lters_Q6.Fig. 21 Receiver PLL circuitsCIRCUIT DESCRIPTIONQ171/N1/RPD+5V+5V+9VQ3+5V208IC55FinLPFLPFQ16+8VLPFQ23+8VQ18REFin+9LV+9LV+9LV+9LVSW SWQ10SW SWQ11Q14Q59Q7318.05~334.00MHzQ8334.05~350.05MHzDiv.ActiveLPFIC6 16 IC30ADC IC91/2IC33 10 IC30ADCQ2,4Q331/N1/RPD+5V+5V+9VQ22+5V208IC115FinLPFLPFLPFLPFLPFQ38+5VQ21+5V+3VQ53+5VAQ35+5VDQ36REFinDiv.Div.ATTATTATTQ2499.0MHz2 749.5MHz