Lattice Semiconductor LatticeMico32 Hardware Developer User Manual

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Lattice Semiconductor LatticeMico32 Hardware Developer User Manual Manual pdf 42 page image

USING THE L ATTICE M ICO S YSTEM S OFTWARE : Creating the Microprocessor Platform in MSB36 LatticeMico32 Hardware Developer User Guide<platform_name>/components/i2cm_opencores/rtl/verilogSee the Synthesis Data Flow Tutorial for step-by-step information aboutsynthesizing designs in Precision RTL Synthesis and Synplify Pro.To create an EDIF file:1. Start the synthesis tool.2. Create a new project in the tool.3. Add the Verilog HDL file output by MSB to the project.4. Set the target device and the options.5. Compile the project and specify the timing objectives.6. Synthesize the design to generate an EDIF (.edn or .edf) file.Design Guidance for PlatformPerformanceSetting preferences and performing static timing analysis can help achievehigher platform design performance or minimize area utilization. The followingdocuments give instructions and examples for setting design constraints: Achieving Timing Closure in FPGA Designs – This tutorial providestechniques for optimizing design performance and demonstrates theinfluence of map and place-and-route preferences. It uses a system-on-chip design that utilizes an OpenRISC 1200 processor and Wishbone on-chip bus. FPGA Design Guide – The chapter "Strategies for Timing Closure" givesinstructions for constraining your design, performing static timing analysis,and floorplanning.Additionally, see the following sections of the Diamond online Help Constraints Reference Guide – This section provides syntax anddescriptions for all preferences Applying Design Constraints – This section consists of guidelines forsetting preferencesGenerating the MicroprocessorBitstreamFor Windows, you now return to Diamond to import the platform source files.You import the Verilog file output by MSB; or for mixed Verilog/VHDL, youimport both the Verilog and VHDL files output by MSB. For Linux, you importthe EDIF file output by the synthesis tool. You also specify the connectionsfrom the microprocessor to the chip pins by importing an .lpf file. You canoptionally perform functional simulation and timing simulation. Primarily, you