C REATING CUSTOM COMPONENTS IN L ATTICE M ICO S YSTEM : Specifying Clock/Reset and External PortsLatticeMico32 Hardware Developer User Guide 61Specifying Clock/Reset and External PortsConnecting the component to the WISHBONE bus enables the LatticeMico32microprocessor to control and access the custom component. The customcomponent has its own unique input and output control signals that must beconnected outside of the platform to the rest of the system. The External Portstab enables these control signals to be defined so that MSB can correctlygenerate a top-level Verilog module. Figure 31 shows the External Ports tabof the Import/Create Custom Components dialog box.This tab continues the task of building a Verilog wrapper around the customcomponent. You use this tab to define the CLK_I, RST_I, and optionalINTR_O control signals. The component port specifies the signal namepresented at the <platform>.v top-level module created by MSB when theplatform is generated.Figure 28: Specifying a Slave Port Connectionmodule MyVerilogComponent (// wishbone interfaceinput [31:0] wb_slv_addr,input [31:0] wb_slv_master_data,input wb_slv_cyc,input wb_slv_stb,input [3:0] wb_slv_sel,input wb_slv_we,output [31:0] wb_slv_slave_data,output wb_slv_ack,output wb_slv_err,output wb_slv_rty,// mandatory clock/reset signalsinput wb_clk,input wb_rst,// external interface (optional)output [15:0] external_out_bus,input [8:0] external_in_bus,input external_in_wire,output external_out_wire,// interrupt signal to the processor(s)output interrupt_signal);endmodule
