153μPD1706213. STANDBYThe standby function is intended to reduce the current drain of the device at backup.13.1 STANDBY BLOCK CONFIGURATIONFig. 13-1 shows the configuration of the standby block.As shown in Fig. 13-1, the standby block is further divided into halt control and clock stop control blocks.The halt control block consists of the halt control circuit, interrupt control block, timer carry FF, and the P0D0 /ADC 2 to P0D 3 /ADC 5 pins. It controls the operation of the CPU (program counter, instruction decoder, and ALUblock).The clock stop control block controls the 8 MHz crystal oscillator, CPU, system register, and control register.Fig. 13-1 Standby Block ConfigurationALUHalt blockInterrupt blockTimer carry FF Halt control circuitHALT hP0D3 /ADC5 pinP0D 2 /ADC4 pinP0D 1 /ADC3 pinP0D 0 /ADC2 pinInput latchProgram counter (PC)Instruction decoderClock stop block System registerCE pin Clock stopcontrol circuitSTOP sControl registerX OUT pinXIN pin Internal clockCPU
