172μPD1706214.2 RESET FUNCTIONPower-on reset is applied when V DD rises from a certain voltage, CE reset is applied when the CE pin risesfrom low level to high level.Power-on reset initializes the program counter, stack, system register and control registers, and executesthe program from address 0000H.CE reset initializes the program counter, stack, system register and some control registers, and executesthe program from address 0000H.The main differences between power-on reset and CE reset are the operation of the control registers thatare initialized and the power failure detection circuit described in Section 14.6.Power-on reset and CE reset are controlled by reset signals IRES, RES, and RESET output from the resetcontrol circuit in Fig. 14-1.Table 14-1 shows the IRES, RES, and RESET signal and power-on reset and CE reset relationship.The reset control circuit also operates when the clock-stop instruction (STOP) described in Chapter 13 isexecuted.Sections 14.3 and 14.4 describe CE reset and power-on reset, respectively.Section 14.5 describes the relationship between CE reset and power-on reset.Table 14-1 Relationship between Internal Reset Signal and Each ResetOutput signalInternal reset signal At CE reset At power- At clock-stop Contents controlled by each reset signalon resetIRES × ll ll Forces the device into the halt state.The halt state is released by the setting of thetimer carry FF.RES × ll ll Initializes some control registers.RESET ll ll ll Initializes the program counter, stack, systemregister, and some control registers.
