NEC VERSA 4000 Service Manual

Also see for VERSA 4000 BATTERY CHARGER WITH AC ADAPTER: Manual Manual Manual Manual

Contents

NEC VERSA 4000 Service Manual Manual pdf 21 page image

Technical Information 1-15Video Controller ArchitectureThe video controller architecture is broken down into several modules. The five significantmodules include the sequencer, CRT controller, graphics controller, attribute controller anddithering engine.For example, the sequencer manages CPU and display memory timing. The CRT controllercontrols sync and timing signals. The graphics controller permits the flow of communicationbetween the CPU data bus and the 32-bit internal data bus. The attribute controller pro-duces a 4-bit wide video data stream that refreshes the display.Diskette Controller, Serial Interface, Parallel InterfaceThe PC87334 chip is a 100-pin plastic Thin Quad Flat Plastic (TQFP) chip. The controllerchanges 8-bit parallel data into serial data and writes the data to the diskette. Conversely,the serial data is transmitted from the diskette into parallel data, where it remains until theread operation takes place.Additional PC8733 chip operations include: ISA compatibility low-power CMOS with enhanced power-down modeKeyboard ControllerThe keyboard controller (M38813E4HP) supports a PS/2-style keyboard, mouse and secu-rity features such as keyboard hot keys and password. Refer to Appendix A for keyboardinterface connector pin assignments.When data is written to the output buffer, the controller generates an interrupt, and requeststhe CPU to receive the data. The controller automatically adds an even parity bit to the datasent and waits for a response. The device must acknowledge that the data was successfullyreceived by sending a response to the controller for each byte of data received.PCMCIA ControllerThe controller (PD6722) interfaces with the ISA bus, PCMCIA card socket and configura-tion registers to provide: memory address mapping, I/O address mapping power management for each PCMICA card socket, controlled through power andRESETDRV control registers the elimination of interrupt conflicts using interrupt steering.