© National Instruments | 5-3TitleShort-Hidden (cross reference text)the rising edge of a source signal. Any out signal state changes occur within 80 ns after the risingor falling edge of the source signal.For information on the internal routing available on the DAQ-STC counter/timers, refer toCounter Parts in NI-DAQmx in the NI-DAQmx Help or the LabVIEW Help for more information.Counter 0 Source SignalYou can select any PFI as well as many other internal signals as the Counter 0 Source(Ctr0Source) signal. The Ctr0Source signal is configured in edge-detection mode on either therising or falling edge. The selected edge of the Ctr0Source signal increments and decrements thecounter value depending on the application the counter is performing.You can export the Ctr0Source signal to the PFI 8/CTR 0 SOURCE pin, even if another PFI isinputting the Ctr0Source signal. This output is set to high-impedance at startup.Figure 5-3 shows the timing requirements for the Ctr0Source signal.Figure 5-3. Ctr0Source Timing RequirementsThe maximum allowed frequency is 20 MHz, with a minimum pulse width of 10 ns high or low.There is no minimum frequency.For most applications, unless you select an external source, the 20MHzTimebase signal or the100kHzTimebase signal generates the Ctr0Source signal.Counter 0 Gate SignalYou can select any PFI as well as many other internal signals like the Counter 0 Gate (Ctr0Gate)signal. The Ctr0Gate signal is configured in edge-detection or level-detection mode dependingon the application performed by the counter. The gate signal can perform many differentoperations including starting and stopping the counter, generating interrupts, and saving thecounter contents.You can export the gate signal connected to Counter 0 to the PFI 9/CTR 0 GATE pin, even ifanother PFI is inputting the Ctr0Gate signal. This output is set to high-impedance at startup.tw = 10 ns minimumtp = 50 ns minimumtptw tw