Chapter 5 CountersE Series User Manual 5-6 ni.comCTR 0 OUT PinWhen the CTR 0 OUT pin is configured as an output, theCtr0InternalOutput signal drives the pin. As an input, CTR 0 OUT candrive any of the RTSI <0..6> signals. CTR 0 OUT is set to high-impedanceat startup. Figure 5-6 shows the relationship of CTR 0 OUT andCtr0InternalOutput.Figure 5-6. CTR 0 OUT and Ctr0InternalOutputCounter 0 Up/Down SignalYou can externally input this signal on the P0.6 pin, but it is not availableas an output on the I/O connector. When you enable externally controlledcount direction, Counter 0 counts down when this pin is at a logic low andcounts up when it is at a logic high. If you are using an external signal tocontrol the count direction, do not use the P0.6 pin for output. If you do notenable externally controlled count direction, the P0.6 pin is free for generaluse.Counter 1 Source SignalYou can select any PFI as well as many other internal signals as the Counter1 Source (Ctr1Source) signal. The Ctr1Source signal is configured inedge-detection mode on either rising or falling edge. The selected edge ofthe Ctr1Source signal increments and decrements the counter valuedepending on the application the counter is performing.You can export the Counter 1 signal to the PFI 3/CTR 1 SOURCE pin, evenif another PFI is inputting the Ctr1Source signal. This output is set tohigh-impedance at startup.Ctr0GateCtr0SourceCtr0Up/DownCounter 0 Ctr0InternalOutputCan Drive RTSI <0..6>,ai/SampleClock,ai/StartTrigger,or other signalsCTR 0 OUTCtr0OutCan Drive RTSI <0..6>
