Nvidia TEGRA DG-04927-001_V01 User Manual

Also see for Tegra 250: Manual Hardware introduction and setup

Nvidia TEGRA DG-04927-001_V01 User Manual Manual pdf 20 page image

Tegra 200 Series Developer Board User GuideDG-04927-001_v01 Advance Information – Subject to Change 20NVIDIA CONFIDENTIAL4.2 ClocksThe Tegra 250 has a large number of internal functional blocks supporting a broad range of interfaces. Each of these has itsown clocking requirements. The RTC (Real Time Clock) and PMC (Power Management Controller) require a 32.768KHz clock,to be provided externally. In addition, a higher frequency reference clock (OSC) is required. This can come from a crystal or anexternal source, and feeds several integrated PLLs that provide a variety of clocking options for the core and I/O blocks. TheTegra 250 clocking scheme is shown in Figure 8.Figure 8. Tegra 250 Clocking Block Diagram4.2.1 32.768KHz ClockThe 32.768KHz clock is provided externally by the PMU. This clock is input on the CLK_32K_IN pin which is referenced to theVDDIO_SYS rail. See the Tegra 200 Series Datasheet (Electrical, Mechanical and Thermal Specifications) for details on therequirements for this clock.4.2.2 Oscillator ClockThe Tegra 200 Series Developer Board utilizes a 12MHz crystal connected to the Tegra 250 XTAL_IN, XTAL_OUT pins togenerate the reference clock internally. A reference circuit is shown in Figure 9.Table 6 contains the requirements for the crystal used, the value of the parallel bias resistor and information to calculate thevalues of the two external load capacitors (CL1 and CL2 ) shown in the circuit.