Nvidia TEGRA DG-04927-001_V01 User Manual

Also see for Tegra 250: Manual Hardware introduction and setup

Nvidia TEGRA DG-04927-001_V01 User Manual Manual pdf 9 page image

Tegra 200 Series Developer Board User GuideDG-04927-001_v01 Advance Information – Subject to Change 9NVIDIA CONFIDENTIAL2.5 LCD InterfaceThe Smartbook Development System routes an 18-bit parallel RGB interface from the Tegra 250 to a Texas InstrumentsSN75LVDS83B LVDS Transmitter which goes to an LVDS panel connector (J7). The connector is a Foxconn GS13307-11230-7F.The controls available for the panel and backlight include: Panel power provided by main 3.3V Buck regulator and enabled by the Tegra 250 GPIO on LCD_PWR2(EN_VDD_PNL) Backlight enable controlled by the Tegra 250 GPIO on pin SDIO3_DAT2 (SDIO block) Backlight PWM controlled by PM3_PWM0 on SDIO3_DAT3 (SDIO block) Backlight power provided from VDD_VBAT (battery or AC/DC adapter) and enabled by the Tegra 250 GPIO onLCD_CS1_N LVDS Transmitter shutdown enabled by Tegra 250 GPIO on pin LCD_PWR02.6 External Display SupportA standard HDMI Type A connector (J18) is provided and supports up to 1080p60Hz operation. The Tegra 200 SeriesDeveloper Board supports Hot Plug Detect by routing the HP_DET line on the HDMI connector to the Tegra 250 HDMI_INT_Ninterrupt pin. The DDC interface is shared between HDMI and the VGA interface, so only one of these displays can beconnected at a time.A standard 15-pin VGA connector (J12) is also provided and supports resolutions up to 1600x1200. The Tegra 200 SeriesDeveloper Board also supports detection of a VGA device connection. This uses the Tegra 250 pin SPI2_SCK on the Audioblock.2.7 AudioThe Tegra 200 Series Developer Board integrates the Wolfson Microelectronics WM8903 Ultra Low Power CODEC for PortableAudio Applications. The Tegra 250 DAP1 interface supporting I2S protocol communicates audio data to/from the CODEC.GEN1_I2C is used for CODEC configuration. The audio subsystem features: Left and Right amplified speaker output via two Wolfson WM9001 amplifiers- Headers for connecting Left (J11)/Right (J21) speakers Stereo headphone jack (J1) Both internal Microphone (J8) and external microphone jack (J2)2.8 USBThe Tegra 250 has three available USB controllers. Controllers #1 and #3 come out on the USB PHYs on the USB1 and USB3pins. Controller #2 can be used for either ULPI or HSIC (only one at a time). All three USB controllers are used on the Tegra200 Series Developer Board.Controller #1USB1 (PHY) is required for Recovery mode and so is brought out to a USB Mini B connector (J3). USB1 is configured as adevice to allow connection to a host PC, typically for flashing images at the factory or possibly in the field.Controller #2USB2 provides a ULPI interface on the Tegra 200 Series Developer Board and connects to an external USB3315 ULPI PHY.The PHY then connects to PCIe Mini-Card 0 (J27) which is intended for a 3G baseband module.Controller #3USB3 (PHY) is routed to an SMSC LAN9514 USB Hub and Ethernet controller. This controller provides one Ethernet interfaceand four USB Host ports. The Tegra 200 Series Developer Board routes the Ethernet signals to a standard RJ-45 jack. Three