Nvidia TEGRA DG-04927-001_V01 User Manual
Also see for Tegra 250: Manual Hardware introduction and setup
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Contents
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Tegra 200 Series Developer Board User GuideDG-04927-001_v01 Advance Information – Subject to Change 29NVIDIA CONFIDENTIAL4.6.2 HDMI HDMI_RSET on the Tegra 250 is tied to ground through a 1KΩ, 1% resistor DDC_SCL/SDA pins are 5V tolerant (no level shifter required). I2C pull-ups connect to 5V supply. HP_DET drives HDMI_INT (interrupt pin) on the Tegra 250 (Also 5V tolerant - no level shifter required).Figure 17: HDMI Connection ExampleTable 11. HDMI PinoutSignal Pin Signal PinHDMI_TXCN AF17 HDMI_TXD1N AC18HDMI_TXCP AG17 HDMI_TXD1P AD18HDMI_TXD0N AE16 HDMI_TXD2N AH18HDMI_TXD0P AE17 HDMI_TXD2P AG184.6.2.1 Unused PinsAny unused signal lines can be left unconnected. If HDMI is not implemented, AVDD_HDMI/HDMI_PLL rails and all signal pinscan be left unconnected. |
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