9.3. CD Servo BlockIC401 : YESAM275PinNo.Port Descriptions I/O (V)1 CVSS1 GND - 02 - - - -3 CVSS2 GND - 04 DVDD1 I/O system (3.3V) power supply - 3.35 A10 Address bus of FLASH ROM O 06 - - - -7 A11 Address bus of FLASH ROM O 3.38 A12 O 3.39 A13 O 3.310 A14 O 3.311 A15 O 3.312 /CVDD1 CORE CPU system (1.6V) powersupply- 1.613 - - - -14 DVSS1 GND - 015 CVSS3 GND - 016 /CVDD2 I/O system (3.3V) power supply - 1.617 - - - -18 - - - -19 READY - - 3.320 /PS FLASH ROM selection signal O 3.321 - - - -22 - - - -23 R/W Lead/light signal to FLASH ROM O 3.324 /MSTRB Memory access signal O 3.325 - - - -26 /MSC - - 3.327 MUTE Mute signal output (H:Mute on) O 028 - - - -29 - - - -30 /HOLD - - 3.331 BIO SUBO input I 032 MP/MC Operation mode setting (external pull-up)I 3.333 DVDD2 I/O system (3.3V) power supply - 3.334 CVSS4 GND - 035 BD R1 GND I 036 - - - -37 CVSS5 GND - 038 - - - -39 - - - -40 DVSS2 GND - 041 CLK C M AUDIO bit clock input I 1.642 SCK Clock input I 3.343 LRCK CMAUDIO L/R identifying signal input I 1.644 CDFS Serial frame sink signal input I 2.645 DATACMAUDIO serial data input I 1.646 - - - -47 SI Serial data input I 048 CLK M C AUDIO bit clock output O 1.649 SCK Clock input I 3.350 CVSS6 GND - 051 - - - -52 CVDD3 CORE CPU system (1.6V) powersupply- 1.653 LRCK MCAUDIO L/R identifying signal output O 1.654 CDFS Serial frame sink signal input I 2.455 - - - -56 DVDD3 I/O system (3.3V) power supply - 3.357 DVSS3 GND - 0PinNo.Port Descriptions I/O (V)58 RESTSWMechanics deck REST SW input I 3.359 DATA MCAUDIO serial data output O 1.660 SO Serial data output O 1.261 - - - -62 - - - -63 /NMI - - 3.364 /INT0 - - 3.365 /INT1 - - 3.366 BLKCK Subcode block clock pulse input I 067 /INT3 - - 3.368 CV DD4 CORE CPU system (1.6V) powersupply- 1.669 SW1 Mechanics deck SW1 input I 070 CVSS7 GND - 071 MCLK Clock output (To Servo DSP) O 3.372 DVSS4 GND - 073 MLD Command load signal output (ToServo DSP)I 3.374 MDATA Command data output (To ServoDSP)O 3.375 DVDD4 I/O system (3.3V) power supply - 3.376 DVSS5 GND - 077 CLK MD1 Clock mode setting (L fixation) I 078 CLK MD2 Clock mode setting (H fixation) I 3.379 CLK MD3 Clock mode setting (L fixation) I -80 - - - -81 SW2 Mechanics deck SW2 input I 082 - - - -83 EMU0 - - 084 EMU/OFF- - 3.385 TDO - - 3.386 TDI - - 087 /TRST - - 3.388 TCK - - 089 TMS - - 3.390 CVSS8 GND - 3.391 CVDD5 CORE CPU system (1.6V) powersupply- 092 HPIENA GND I 1.693 DVSS6 GND - 094 - - - -95 CLKENA Oscillation output Cainabl signal O 3.396 X1 Crystal Connection O 097 X2/CLKIN Crystal Connection I 098 RS Reset signal input I 199 D0 Data base of FLASH ROM I/O 3.4100 D1 I/O 0101 D2 I/O 0102 D3 I/O 0103 D4 I/O 0104 D5 I/O 0105 A16 Address bus of FLASH ROM O 0106 DVSS7 GND - 0107 A17 Address bus of FLASH ROM O 3.3108 A18 O 0109 A19 Address bus of FLASH ROM O 0110 A20 O 0111 CVSS9 GND - 0112 DVDD5 I/O system (3.3V) power supply - 3.3113 D6 Data bus of FLASH ROM I/O 0114 D7 I/O 0115 D8 I/O 0116 D9 I/O 0117 D10 I/O 06CQ-C1401U / CQ-C1301U