I - 3Chapter 1 OverviewHardware Functions1-2 Hardware FunctionsCPU Core MN101C Core- LOAD-STORE architecture (3-stage pipeline)- Half-byte instruction set / Handy addressing- Memory addressing space is 256 KB- Minimum instructions execution time (3.0 V to 3.6 V for Flash version)High speed oscillation[normal] 0.10 μs / 20 MHz (2.5 V to 3.6 V)0.20 μs / 10 MHz (2.1 V to 3.6 V)0.50 μs / 4 MHz (1.8 V to 3.6 V)[2x-speed] 0.119 μs / 8.39 MHz (2.5 V to 3.6 V)Low speed oscillation 61.04 μs / 32.768 kHz (1.8 V to 3.6 V)- Operation modesNORMAL mode ( High speed oscillation )SLOW mode ( Low speed oscillation )HALT modeSTOP mode(The operation clock can be switched in each mode.)Memory bank Data memory space expansion by bank form (4 banks unit : 64 KB / 1 bank)- Bank for source address / Bank for destination addressROM correction Max.3 parts in program can be correctedInternal memory ROM 48 KB (Flash version 128 KB)RAM 3 KB (Flash version 6 KB)Interrupts 17 Internal interrupts- Incorrect code execution interrupt and Watchdog timer interrupt< Timer interrupts >- Timer 0 interrupt (8-bit timer)- Timer 1 interrupt (8-bit timer)- Timer 4 interrupt (8-bit timer)- Timer 5 interrupt (8-bit timer)- Timer 6 interrupt (8-bit timer)- Time base interrupt (8-bit timer)- Timer 7 interrupt (16-bit timer)- Match interrupt for Timer 7 compare register 2
