Chapter 2 CPU BasicsII - 16 Bus Interface2-3-2 Control RegistersBus interface is controlled by these 8 bytes of registers : the memory control register (MEMCTR),memory area control register (AREACTR) and bus mode control register (CSMDn).Memory Control Register (MEMCTR)Figure 2-3-2 Memory Control Register (MEMCTR: x'03F01' R/W)EXW1 to 0, EXWH and IOW1 to 0 flags of the memory control register (MEMCTR) need notto be set. Set wait cycle with bus mode control register (CSMDn).7 0MEMCTR EXMEMIOW1 IOW0 ( At reset : 1 1 0 0 1 0 1 1 )EXWH EXW1 EXW0EXW1 to 0 Fixed wait cycles0 00 11 01 1No wait cycles1 wait cycle2 wait cycles3 wait cyclesEXWH Fixed wait cycle mode or handshake mode0 Handshake modeFixed wait cycle mode1Bus cycle at20 MHz oscillation100 ns150 ns200 ns250 nsIOW1 to 0 Wait cycles whenaccessing special register area0 00 11 01 1No wait cycles1 wait cycle2 wait cycles3 wait cyclesBus cycle at20 MHz oscillation100 ns150 ns200 ns250 nsEXMEM Set always to "0"IVBMIVBM Base address setting for interrupt vector table0 Interrupt vector base = x'04000'Interrupt vector base = x'00100'16 4 3 15 2IRWEIRWE Software write enable flag for interrupt request flag0Software write disableEven if data is written to each interrupt controlregister (xxxICR), the state of the interruptrequest flag (xxxIR) will not change.Software write enable1Don't careDon't careDon't care
