User’s Manual 143• /SLAVEATTN—This line is set low (asserted) if the slave writes to the SPD0R register.This line is set high if the master writes anything to the slave status register. This line isusually connected to cause the master to be interrupted when it goes low.The data lines of the slave port are shared with parallel port A that uses the same packagepins. The slave port can be enabled, and parallel port A be disabled, by storing an appro-priate code in the slave port control register (SCR). After the processor is reset, all thepins belonging to the slave interface are configured as parallel-port inputs unless(SMODE1, SMODE0) are set to (0,1), in which case the slave port is enabled after resetand the slave starts the cold-boot sequence using the slave port.13.1 Hardware Design of Slave Port InterconnectionFigure 13-4 shows a typical circuit diagram for connecting two slave Rabbits to a masterRabbit. The designer has the option of cold-booting the slave and downloading the pro-gram to RAM on each cold start. Another option is to configure the slave with both RAMand flash memory. In this case, the slave will only have the program downloaded formaintenance or upgrades. Usually, the flash would not be written to on every startupbecause of the limited number of lifetime writes to flash memory. The slaves’ reset inFigure 13-4 is under the program control of the master. If the master is reset, the slave willalso be reset because the master’s drive of the reset line will be lost on reset and the pull-down resistor will pull the slaves’ resets low. This may be undesirable because it forcesthe slave to crash if the master crashes and has a watchdog timeout.13.2 Slave Port RegistersThe slave port registers are listed in Table 13-1. These registers, each of which is actuallytwo separate registers, one for read and one for write, are accessible to the slave at the I/Oaddresses shown in the table and they are accessible to the master at the external addressshown which specifies the value of the slave address (SA0, SA1) input to the slave whenthe master reads or writes the registers. The register that can be written by the slave canonly be read by the master and vice versa. If one side were to attempt to read a register atthe same time that the other side attempted to write the register the result of the read couldbe scrambled. However, the protocols and handshaking bits used in communication arenormally such that this never happens.Table 13-1. Slave Port RegistersRegister Mnemonic InternalAddressExternalAddressSlave Port Data x RegisterSPD0R 0x20 0SPD1R 0x21 1SPD2R 0x22 2Slave Port Status Register SPSR 0x23 3Slave Port Control Register SPCR 0x24 N.A.
