58 Rabbit 2000 Microprocessor5.4 Bus TimingThe external bus has essentially the same timing for memory cycles or I/O cycles. Amemory cycle begins with the chip select and the address lines. One clock later, the out-put enable is asserted for a read. The output data and the write enable are asserted for awrite.Figure 5-4. Bus Timing Read and WriteIn some cases, the timing shown in Figure 5-4 may be prefixed by a false memory accessduring the first clock, which is followed by the access sequence shown in Figure 5-4. Inthis case, the address and often the chip select will change values after one clock andassume the final values for the memory to be actually accessed. Output enable and writeenable are always delayed by one clock from the time the final, stable address and chipselect are enabled. Normally the false memory access attempts to start another instructionaccess cycle, which is aborted after one clock when the processor realizes that a read dataor write data bus cycle is needed. The user should not attempt a design that uses the chipselect or a memory address as a clock or state changing signal without taking this into con-sideration.Address (20 for memory, 16 for I/O)T1 Tw T2/IOCSn or /CSnData for readvalid/OEn or /IORD and /BUFEN (/BUFEN rd or wr)Data for write 3-s drive starts at end of T1/WEn or /IOWRNotes:Read may have no wait states.Write cycles and I/O read cycles have at least 1 wait state. Clockmay be asymmetric if clock doubler used. I/O chip select avail-able on port E as option.
