RadiSys EPC-2 Hardware Reference Manual
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that the EPC-2 can access the global memory with the same addresses as used byother processors without needing to understand that the memory is actually on-board.This ability is also useful in system checkout (i.e., checking operation of thebackplane) and in giving an EPC-2 program the ability to view its memory in.i.big endian; format.Read-Modify-Write Operations.i.RMW cycle;Read-modify-write cycle;The EPC-2 provides synchronizationintegrity in its local DRAM between accesses from the 386 into the DRAM and RMWVXI accesses from other masters into the DRAM.When a VXIbus slave read access occurs to the local DRAM, the EPC-2 watches theVXIbus data and address strobes to determine if the cycle is an RMW cycle. Ifit is, accesses by the 386 are held up until the terminating access of the RMWcycle occurs.When the 386 performs a locked access (e.g., via an instruction using the.i.LOCK instruction prefix;) to the local DRAM, VXIbus read and RMW slaveaccesses are held up until the last locked access completes..i.self accesses;One more case of interest is when the EPC-2 performs a lockedaccess that results in a self access. These function correctly (i.e., as if theaccess were not a self access), providing that operating-system tables (e.g.,.i.page tables;) that are accessed by the 386 by implicit locked accesses arenot mapped into VXI. This would only be a concern for user-written operatingsystems.VXIbus Interrupt AcknowledgementWhen it asserts an interrupt, the EPC-2 formulates a .i.status/ID; value that istransmitted on the bus as the response to a matching .i.interruptacknowledge;ment cycle. The EPC-2 acts as a D16 interrupter. The lower eightbits of the status/ID value are the EPC-2's ULA, and the source for the uppereight bits is specified by the IST bit in the .i.MSC; .i.module status/controlregister;.Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com |
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