Realtek RTD2120K Manual
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Realtek RTD2120-seriesconfidential 21Name Bits Read/Write Reset State CommentsADC1_CONV_DATA7:2 R 3F Converted data of ADC1reserved 1:0 -- 00Register::ADC2_convert_result 0xFF0EName Bits Read/Write Reset State CommentsADC2_CONV_DATA7:2 R 3F Converted data of ADC2reserved 1:0 -- 00Register::ADC3_convert_result 0xFF0FName Bits Read/Write Reset State CommentsADC3_CONV_DATA7:2 R 3F Converted data of ADC3reserved 1:0 -- 00PLLRTD2120 contains a PLL to make the whole chip operate at higher or lower speed for differentdemands. After reset, RTD2120 uses crystal frequency as the system clock. User can program the PLLto operate at the desired frequency and select system clock to PLL output by setting MCU_CLK_SEL.RTD2120 will switch system clock to PLL output only when PLL is stable. Moreover, the divider isglitch free so user can modify its value at any time.For normal operation, user must choose the crystalwhose frequency is between 11M and 27MHz . Besides, VCO frequency must be programmedbetween 40M and 80MHz.Note: Fvco = Xtal *(M/N) , where M=M_code+1, N=N_code+1.Crystal11M~27MHz NDIVPFD VCOM40M~80MHzPUMPMCU_CLK_SELMCU_CLK |
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