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S3C2501X
Samsung S3C2501X User Manual
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Samsung S3C2501X User Manual
Table of content
Contents
important notice
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
list of tables
Overview
Features
Block Diagram
Package Diagram
Pin Assignment
Signal Description
Pad Type
Special Registers
Memory Formats
Instruction Length
Registers
Register Organization in ARM State
Register Organization in THUMB State
The Relationship Between ARM and THUMB State Registers
Accessing Hi-Registers in THUMB State
The Condition Code Flags
Exceptions
Exception Entry/Exit Summary
Abort
Software Interrupt
Exception Priorities
Interrupt Latencies
Introduction for ARM940T
ARM940T Block Diagram
About The ARM940T Programmer's Model
Data Abort Model
ARM940T CP15 Registers
Instruction Set Summay
Instruction Summary
The Condition Field
Branch and Exchange (BX)
Branch and Branch with Link (B, BL)
Assembler Syntax
Data Processing
CPSR Flags
Shifts
Logical Shift Right
Rotate Right
Immediate Operand Rotates
Instruction Cycle Times
PSR Transfer (MRS, MSR)
PSR Transfer
Reserved Bits
Multiply and Multiply-Accumulate (MUL, MLA)
Multiply Long and Multiply-Accumulate Long (MULL, MLAL)
Single Data Transfer (LDR, STR)
Offsets and Auto-Indexing
Little-Endian Offset Addressing
Use of R15
Halfword and Signed Data Transfer (LDRH/STRH/LDRSB/LDRSH)
Half-Word Load and Stores
Block Data Transfer (LDM, STM)
Addressing Modes
Pre-Increment Addressing
Use of R15 as the Base
Inclusion of the Base in the Register List
Single Data Swap (SWP)
Data Aborts
Software Interrupt (SWI)
Coprocessor Data Operations (CDP)
Coprocessor Data Transfers (LDC, STC)
Coprocessor Register Transfers (MRC, MCR)
Transfers to R15
Undefined Instruction
Instruction Set Examples
Pseudo-Random Binary Sequence Generator
Loading a Word From an Unknown Alignment
Thumb Instruction Set Format
Opcode Summary
Format 1: Move Shifted Register
Format 2: Add/Subtract
Format 3: Move/Compare/Add/Subtract Immediate
Format 4: ALU Operations
Format 5: Hi-Register Operations/Branch Exchange
Using R15 as an Operand
Format 6: PC-Relative Load
Format 7: Load/Store With Register Offset
Format 8: Load/Store Sign-Extended Byte/Half-Word
Format 9: Load/Store with Immediate Offset
Format 10: Load/Store Half-Word
Format 11: SP-Relative Load/Store
Format 12: Load Addres
Format 13: Add Offset to Stack Pointer
Format 14: Push/Pop Registers
Format 15: Multiple Load/Store
Format 16: Conditional Branch
Format 17: Software Interrupt
Format 18: Unconditional Branch
Format 19: Long Branch With Link
General Purpose Signed Divide
Division by a Constant
Address Map
Remap of Memory Space
Arbitration Scheme
Priority Groups of S3C2501X
AHB Programmable Priority Registers
Problem Solvings with Programmable Round-Robin
Clock Configuration
Shows the Clock Generation Logic of the S3C2501X
System Configuration Special Registers
System Configuration Register
Product Code and Revision Number Register
Clock Control Register
Peripheral Clock Disable Register
Clock Status Register
Core PLL Control Register
System Bus PLL Control Register
PHY PLL Control Register
Memory Map
Memory Bank Address map
Bus Interface Signals
Memory Controller Bus Signals
Endian Modes
Ext I/O Bank Controller
External Device Connection
bit ROM, SRAM and Flash Basic Connection (8-bit Memory x 2)
bit SRAM Basic Connection
bit ROM and Flash Basic Connection
bit ROM Basic Connection 2
bit SRAM Basic Connection 2
ROM & SRAM with Muxed Address & Data Bus Connection
Ext. I/O Bank Controller Special Register
BnCON
Bank n Control (BnCON) Register Configuration
Muxed Bus Control (MUXBCON) Register Configuration
Wait Control (WAITCON) Register Configuration
Timing Diagram
Write Timing Diagram 1
Read Timing Diagram 2
Write Timing Diagram 2
Read after Write at the Same Bank (COHDIS = 1)
Read Timing Diagram (Muxed Bus)
Write Timing Diagram (Muxed Bus)
Write Timing Diagram (nEWAIT)
Write Timing Diagram (nREADY)
SDRAM Controller
SDRAM Size and Configuration
Address Mapping
SDRAM Commands
External Data Bus Width
Basic Operation
SDRAM Special Registers
SDRAM Configuration Register 0
SDRAM Command Register
SDRAM Refresh Timer Register
SDRAM Write Buffer Time-out Register
SDRAM Controller Timing
Single Read Operation (CAS Latency=3)
Single Write Operation
Burst Read Operation (CAS Latency = 2)
Burst Read Operation (CAS Latency = 3)
Burst Write Operation
Functional Description
General Characteristics
Data Validity
Data Transfer Operations
Data Transfer Format
Control Status Register
I 2 C Control Status Register
Shift Buffer Register
Prescaler Counter Register
MAC Function Blocks
Physical Layer Entity (PHY)
The MAC Receiver Block
Flow Control Block
Data Structure of Tx Buffer Descriptor
Data Structure of Rx Buffer Descriptor
Data Structure of the Receive Frame
Ethernet Controller Special Registers
BDMA Relative Special Register
MAC Relative Special Register
Ethernet Operations
Fields of an IEEE802.3/Ethernet Frame
CSMA/CD Transmit Operation
Timing for Transmission without Collision
Timing for Transmission with Collision in Preamble
Receiving Frame without Error
CSMA/CD Receive Operation
The MII Station Manager
Full-Duplex Pause Operations
Error Signalling
Timing Parameters for MII Transactions
DES/3DES Block Diagram
DES/3DES Special Registers
DES/3DES Control Register
DES/3DES Status Register
DES/3DES Interrupt Enable Register
DES/3DES Key 2 Left/Right Side Register
DES/3DES Input/Output Data FIFO Register
DES/3DES Operation
Performance Calculation Guide
GDMA Controller Block Diagram
GDMA Special Registers
GDMA Programmable Priority Registers
GDMA Control Registers
GDMA Control Register
GDMA Source/Destination Address Registers
GDMA Transfer Count Registers
GDMA Run Enable Registers
GDMA Interrupt Pending Register
GDMA Mode Operation
DES Mode
Data Transfer Modes
GDMA Transfer Timing Data
Single and One Data Burst Mode
Single and Four Data Burst Mode
Block and One Data Burst Mode
Block and Four Data Burst
Console UART Block Diagram
Console UART Special Registers
Console UART Control Registers
Console UART Control Register
Console UART Status Registers
Console UART Status Register
Console UART Interrupt Enable Register
UART Transmit Data Register
UART Receive Data Register
UART Baud Rate Divisor Register
Console UART Baud Rate Examples
UART Control Character Register 1 and 2
Interrupt-Based Serial I/O Transmit and Receive Timing Diagram
Serial I/O Frame Timing Diagram (Normal Console UART)
Infra-Red Receive Mode Frame Timing Diagram
High-Speed UART Block Diagram
High-Speed UART Special Registers
High-Speed UART Control Registers
High-Speed UART Control Register
High-Speed UART Status Registers
High-Speed UART Status Register
High-Speed UART Interrupt Enable Register
High-Speed UART Transmit Buffer Register
High-Speed UART Receive Buffer Register
High-Speed UART Baud Rate Divisor Register
High-Speed UART Baud Rate Examples
High-Speed UART Control Character 1 Register
High-Speed UART Control Character 2 Register
AutoBaud Boundary Register Range
High-Speed UART Autobaud Table Regsiter
High-Speed UART Operation
When CTS Signal Level is High During Transmit Operation
Software Flow Control
DMA-Based Serial I/O Timing Diagram (Tx Only)
Serial I/O Frame Timing Diagram (Normal High-Speed UART)
I/O Port Special Register
I/O Port Mode Registers 1/2
I/O Port Function Control Register
I/O Function Control Register 1
I/O Function Control Register 2
I/O Port Control Register for GDMA
I/O Port Control Register for External Interrupt
I/O Port External Interrupt Clear Register
I/O Port Data Register
Interrupt Sources
Interrupt Controller Special Registers
Internal Interrupt Mode Register
Interrupt Mask Registers
Internal Interrupt Mask Register
External Interrupt Mask Register
Interrupt Priority Registers
Interrupt Offset Register
Interrupt by Priority Register
Interval Mode Operation
Timer Operation Guidelines
Timer Mode Register
Timer Data Registers
Timer Count Registers
Timer Interrupt Clear Registers
Watchdog Timer Register
DC Electrical Specifications
AC Electrical Characteristics
mechanical data
BGA-2727-AN Package Dimensions
S3C2501X
32-BIT RISC
MICROPROCESSOR
USER'S MANUAL
Revision 1
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