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Samsung S3C80A5B User Manual
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Samsung S3C80A5B User Manual
Table of content
Contents
important notice
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Overview
Features
Block Diagram
Pin Assignments
Pin Descriptions
Pin Circuits
Pin Circuit Type 2 (Port 1)
Pin Circuit Type 4 (P2.1)
Program memory (ROM)
Register Architecture
Internal Register File Organization
Register Page Pointer (PP)
Register Set 1
Prime Register Space
Working Registers
Using the Register Pointers
Non-Contiguous 16-Byte Working Register Block
Register Addressing
Register File Addressing
Common Working Register Area (C0H–CFH)
Bit Working Register Addressing
Bit Working Register Addressing Example
System and User Stacks
Standard Stack Operations Using PUSH and POP
Register Addressing Mode (R)
Indirect Register Addressing Mode (IR)
Indirect Register Addressing to Program Memory
Indirect Working Register Addressing to Register File
Indirect Working Register Addressing to Program or Data Memory
Indexed Addressing Mode (X)
Indexed Addressing to Program or Data Memory with Short Offset
Indexed Addressing to Program or Data Memory
Direct Address Mode (DA)
Direct Addressing for Call and Jump Instructions
Indirect Address Mode (IA)
Relative Address Mode (RA)
Immediate Mode (IM)
Mapped Registers (Set 1)
Register Description Format
Basic Timer Control Register
Counter A Control Register
System Clock Control Register
External Memory Timing Register
System Flags Register
Interrupt Mask Register
Instruction Pointer (High Byte)
Interrupt Priority Register
Interrupt Request Register
Port 0 Control Register (High Byte)
Port 0 Control Register (Low Byte)
Port 0 Pull-up Resistor Enable Register
Port 1 Control Register (High Byte)
Port 1 Control Register (Low Byte)
Port 2 Control Register
Register Page Pointer
Register Pointer 0
Stack Pointer (Low Byte)
System Mode Register
Timer 0 Control Register
Timer 1 Control Register
Interrupt Types
S3C80A5B Interrupt Structure
Interrupt Vector Addresses
S3C80A5B Interrupt Vectors
Enable/Disable Interrupt Instructions (EI, DI)
Interrupt Processing Control Points
Peripheral Interrupt Control Registers
System Mode Register (SYM)
Interrupt Mask Register (IMR)
Interrupt Priority Register (IPR)
Interrupt Request Register (IRQ)
Interrupt Pending Function Types
Interrupt Source Polling Sequence
Generating interrupt Vector Addresses
Instruction Group Summary
Flags Register (FLAGS)
Flag Descriptions
Instruction Set Notation
Instruction Notation Conventions
Opcode Quick Reference
Condition Codes
Instruction Descriptions
ADC Add with Carry
AND Logical AND
BAND Bit AND
BCP Bit Compare
BITC Bit Complement
BITR Bit Reset
BITS Bit Set
BTJRF Bit Test, Jump Relative on False
BTJRT Bit Test, Jump Relative on True
BXOR Bit XOR
CALL Call Procedure
CCF Complement Carry Flag
CLR Clear
COM Complement
CP Compare
CPIJE Compare, Increment, and Jump on Equal
CPIJNE Compare, Increment, and Jump on Non-Equal
DA Decimal Adjust
DEC Decrement
DECW Decrement Word
DI Disable Interrupts
DIV Divide (Unsigned)
DJNZ Decrement and Jump if Non-Zero
EI Enable Interrupts
ENTER Enter
EXIT Exit
IDLE Idle Operation
INC Increment
INCW Increment Word
IRET Interrupt Return
JR Jump Relative
LDB Load Bit
Load Memory
Load Memory and Decrement
Load Memory and Increment
Load Memory with Pre-Decrement
Load Memory with Pre-Increment
Load Word
Multiply (Unsigned)
Next
No Operation
Logical OR
Pop from Stack
Pop User Stack (Decrementing)
Pop User Stack (Incrementing)
Push to Stack
Push User Stack (Decrementing)
Push User Stack (Incrementing)
Reset Carry Flag
Return
Rotate Left
Rotate Left through Carry
Rotate Right
Rotate Right through Carry
Select Bank 0
Select Bank 1
Subtract with Carry
Set Carry Flag
Shift Right Arithmetic
Set Register Pointer
Stop Operation
Subtract
Swap Nibbles
Test Complement under Mask
Test under Mask
Wait for Interrupt
Logical Exclusive OR
Clock Status During Power-Down Modes
System Clock Control Register (CLKCON)
System Reset
Interrupt With Reset(INTR)
System Reset Operation
Hardware Reset Values
Power-Down Modes
To Divide STOP Mode Releasing and POR
Idle Mode
Summary Table of Stop Mode, and Idle Mode
Port Data Registers
PORT
Port 0 Interrupt Enable Register (P0INT)
Port 0 External Interrupt Control Register (P0INT)
Port 1 Low-Byte Control Register (P1CONL)
Port 2 Data Register (P2)
Module Overview
Basic Timer Function Description
Timer 0 Function Description
Simplified Timer 0 Function Diagram: PWM Mode
Basic Timer and Timer 0 Block Diagram
Configuring the Basic Timer
Programming Timer 0
Timer 1 Overflow Interrupt
Timer 1 Block Diagram
Timer 1 Control Register (T1CON)
Timer 1 Registers
Counter A Block Diagram
Counter A Control Register (CACON)
Counter A Pulse Width Calculations
Counter A Output Flip-Flop Waveforms in Repeat Mode
To Generate 38 kHz, 1/3duty Signal Through P2.1
To Generate a One Pulse Signal Through P2.1
Absolute Maximum Ratings
Characteristics of Low Voltage Detect Circuit
Input Timing for External Interrupts (Port 0)
Operating Voltage Range of S3C80A5B
Pin SDIP Package Mechanical Data
USER'S MANUAL ERRATA
This document contains the corrections of errors,
typos and omissions in the following document.
Samsung 8-bit CMOS
S3C80A5B
Microprocessor
User's Manual
Document Number: 21.1-S3-C80A5B-082005
Publication: August 2005
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