Tait TP9100 Service Manual

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TP9100 Service Manual Description 45© Tait Electronics Limited May 2005The FCL generates an output of 13.012MHz±4kHz. Initially a voltagecontrolled crystal oscillator (VCXO) produces a quasi-regulated frequency inthe required range. The VCXO output is fed to a mixer where it is mixed withthe 13.000MHz TCXO frequency. The mixer, after low-pass filtering toremove unwanted products, produces a frequency of 12kHz nominally. This isconverted to digital form and transported to the frequency control block in thecustom logic.The frequency control block compares the mixer output frequency to areference generated by the digital clock and creates a DC error signal.A programmed offset is also added. This error signal is converted to analogform and used to control the VCXO frequency and reduce the initial error.Once settled, the loop “locks” to the TCXO frequency with a programmedoffset frequency. The FCL output therefore acquires the TCXO's frequencystability.The FCL may be run in an open-loop configuration for short durations toincrease the response time of the power-save modes.Modulation The full bandwidth modulation signal is obtained from the DSP in digitalform at a sample rate of 48kHz. In traditional dual-point modulationsystems the modulation is applied, in analog form, to both the frequencyreference and the VCO in the RF PLL, combining to produce a flatmodulation response down to DC. Reference modulation is usually applieddirectly to the TCXO.The frequency reference is generated by the FCL, which itself requires dual-point modulation injection to allow modulation down to DC. With anothermodulation point required in the RF PLL, this system therefore requirestriple-point modulation. The modulation signals applied to the FCL are indigital form while for the RF PLL (VCO) the modulation signal is appliedin analog form. The modulation cross-over points occur at approximately30 and 300Hz as determined by the closed loop bandwidths of the FCL andRF PLL respectively.FrequencyGeneration The RF PLL has a frequency resolution of 25kHz. Higher resolutioncannot be achieved owing to acquisition-time requirements and so for anygiven frequency the error could be as high as ±12.5kHz. This error iscorrected by altering the reference frequency to the RF PLL. The FCLsupplies the reference frequency and is able to adjust it up to ±300ppm withbetter than 0.1ppm resolution (equivalent to better than 50Hz resolution atthe RF frequency). The FCL offset will usually be different for receive andtransmit modes.Fast FrequencySettling Both the FCL and RF PLL employ frequency-acquisition speed-uptechniques to achieve fast frequency settling. The frequency-acquisitionprocess of the FCL and RF PLL is able to occur concurrently with minimalloop interaction owing to the very large difference in frequency step sizebetween the loops.