Xilinx DPU IP Product Manual
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Contents
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Chapter 4: Clocking and ResetsDPU IP Product Guide www.xilinx.com 27PG338 (v1.2) March 26, 2019ResetThere are three input clocks for the DPU IP, each of which has a corresponding reset. You mustguarantee each pair of clocks and resets is generated in a synchronous clock domain. If the relatedclocks and resets are not matched, the DPU might not work properly. A recommended solution is toinstantiate a Processor System Reset IP to generate a matched reset for each clock. The referencedesign is shown in Figure 16.Figure 16: Reference Design for ResetsSend Feedback |
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