Xilinx DPU IP Product Manual

Xilinx DPU IP Product Manual Manual pdf 33 page image

DPU IP Product Guide www.xilinx.com 33PG338 (v1.2) March 26, 2019Chapter 6: Example DesignIntroductionThe Xilinx® DPU targeted reference design (TRD) provides instructions on how to use DPU with a XilinxSoC platform to build and run deep neural network applications. The TRD uses the Vivado® IPintegrator flow for building the hardware design and Xilinx Yocto PetaLinux flow for software design.The Zynq® UltraScale+™ MPSoC platform is used to create this TRD. It can also be used for a Zynq-7000 SoC platform with the same flow.This appendix describes the architecture of the reference design and provides a functional descriptionof its components. It is organized as follows:• DPU TRD Overview provides a high-level overview of the Zynq UltraScale+ MPSoC devicearchitecture, the reference design architecture, and a summary of key features.• Hardware Design Flow gives an overview of how to use Xilinx Vivado Design Suite to generatethe reference hardware design.• Software Design Flow describes the design flow of project creation in the PetaLinuxenvironment.• Demo Execution describes how to run the application created by the TRD.DPU TRD OverviewThe TRD creates an image classification application running a popular deep neural network model,Resnet50, on a Xilinx UltraScale+ MPSoC device. The overall functionality of the TRD is partitionedbetween the Processing System (PS) and Programmable Logic (PL), where DPU resides for optimalperformance.The following figure shows the TRD block diagram. The host communicates with the ZCU102 boardthrough Ethernet or UART port. The input images for a TRD are stored in an SD card. When the TRD isrunning, the input data is loaded into DDR memory, then DPU reads the data from the DDR memoryand writes the results back to DDR memory. The result displays on the host screen from the APUthrough Ethernet or UART port.Send Feedback