Xilinx KC705 User Manual
Also see for KC705: User guideUser guideGetting startedUser guide
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KC705 Evaluation Board 28UG810 (v1.8) March 20, 2018 www.xilinx.comChapter 1: KC705 Evaluation Board FeaturesClock GenerationThere are five clock sources available for the FPGA fabric on the KC705 board (refer toTable 1-8).Table 1-9 lists the pin-to-pin connections from each clock source to the FPGA.Table 1-8: KC705 Board Clock SourcesClock Name Reference DescriptionSystem Clock U6 SiT9102 2.5V LVDS 200 MHz Fixed Frequency Oscillator (Si Time). SeeSystem Clock Source, page 29.User ClockU45Si570 3.3V LVDS I2C Programmable Oscillator(Silicon Labs). Default power-on frequency 156.250 MHz. SeeProgrammable User Clock Source, page 29.User SMA Clock(differential pair) J11 USER_SMA_CLOCK_P (net name).See User SMA Clock Input, page 30.J12 USER_SMA_CLOCK_N (net name)See User SMA Clock Input, page 30GTX SMA REF Clock(differential pair) J16 SMA_MGT_REFCLK_P (net name).See GTX SMA Clock Input, page 31.J15 SMA_MGT_REFCLK_N (net name).See GTX SMA Clock Input, page 31.Jitter AttenuatedClock U70Si5324C LVDS precision clock multiplier/jitter attenuator (SiliconLabs).See Jitter Attenuated Clock, page 32.Table 1-9: Clock Source to FPGA U1 ConnectionsClock Source Pin Schematic Net Name I/O Standard U1 FPGA PinU6.5 SYSCLK_N LVDS AD11U6.4 SYSCLK_P LVDS AD12U45.5 USER_CLOCK_N LVDS_25 K29U45.4 USER_CLOCK_P LVDS_25 K28J12.1 USER_SMA_CLOCK_N LVDS_25 K25J11.1 USER_SMA_CLOCK_P LVDS_25 L25J15.1 SMA_MGT_REFCLK_N N/A (MGT REFCLK INPUT) J7J16.1 SMA_MGT_REFCLK_P N/A (MGT REFCLK INPUT) J8U70.29 Si5326_OUT_N N/A (MGT REFCLK INPUT) L7U70.28 Si5326_OUT_P N/A (MGT REFCLK INPUT) L8Send Feedback |
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