Xilinx KC705 User Manual

Also see for KC705: User guide User guide Getting started User guide

Contents

Xilinx KC705 User Manual Manual pdf 88 page image

KC705 Evaluation Board 88UG810 (v1.8) March 20, 2018 www.xilinx.comAppendix CMaster Constraints File ListingThe KC705 board Xilinx® design constraints (XDC) file template provides for designstargeting the KC705 board. Net names in the constraints listed below correlate with netnames on the latest KC705 board schematic. Users must identify the appropriate pins andreplace the net names below with net names in the user RTL. See Vivado Design Suite UserGuide: Using Constraints (UG903) [Ref 26] for more information.Users can refer to the XDC files generated by tools such as Memory Interface Generator(MIG) for memory interfaces and Base System Builder (BSB) for more detailed I/O standardsinformation required for each particular interface. The FMC connectors J2 and J22 areconnected to 2.5V V cco banks. Because each FMC card implements customer-specificcircuitry, the FMC bank I/O standards must be uniquely defined by each customer.Note: The constraints file listed in this appendix might not be the latest version. Always refer to theKintex-7 KC705 Evaluation Kit product page Doc & Designs tab for the latest versions of the FPGApins constraints files (XDC files). Choose the Xilinx tools link. In the search box, search for KC705Master XDC File.KC705 Board XDC Listing#CLOCKS#SYSCLKset_property PACKAGE_PIN AD11 [get_ports SYSCLK_N]set_property IOSTANDARD LVDS [get_ports SYSCLK_N]set_property PACKAGE_PIN AD12 [get_ports SYSCLK_P]set_property IOSTANDARD LVDS [get_ports SYSCLK_P]#USERCLKset_property PACKAGE_PIN K29 [get_ports USER_CLOCK_N]set_property IOSTANDARD LVDS_25 [get_ports USER_CLOCK_N]set_property PACKAGE_PIN K28 [get_ports USER_CLOCK_P]set_property IOSTANDARD LVDS_25 [get_ports USER_CLOCK_P]#USER SMA CLOCKset_property PACKAGE_PIN K25 [get_ports USER_SMA_CLOCK_N]set_property IOSTANDARD LVDS_25 [get_ports USER_SMA_CLOCK_N]set_property PACKAGE_PIN L25 [get_ports USER_SMA_CLOCK_P]set_property IOSTANDARD LVDS_25 [get_ports USER_SMA_CLOCK_P]#SI5326set_property PACKAGE_PIN L7 [get_ports SI5326_OUT_C_N]set_property PACKAGE_PIN L8 [get_ports SI5326_OUT_C_P]Send Feedback