Xilinx ML605 Hardware User's Manual

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22 www.xilinx.com ML605 Hardware User GuideUG534 (v1.9) February 26, 2019Chapter 1: ML605 Evaluation BoardThe Memory Interface Generator (MIG) tool guidelines specify a set of U1 FPGA “NoConnect” pins. These should be added to the UCF as CONFIG PROHIBIT pins as follows:CONFIG PROHIBIT = H22;CONFIG PROHIBIT = F21;CONFIG PROHIBIT = B20;CONFIG PROHIBIT = F19;CONFIG PROHIBIT = C13;CONFIG PROHIBIT = M12;CONFIG PROHIBIT = L13;CONFIG PROHIBIT = K14;CONFIG PROHIBIT = F25;CONFIG PROHIBIT = C29;CONFIG PROHIBIT = C28;CONFIG PROHIBIT = D24;See the Micron Technology, Inc. website for more information [Ref 26].In addition, see the Virtex-6 FPGA Memory Interface Solutions User Guide (UG406) [Ref 6]and the Virtex-6 FPGA Memory Resources User Guide (UG363) [Ref 9].3. 128 Mb Platform Flash XLA 128 Mb Xilinx XCF128X-FTG64C Platform Flash XL device is used with an onboard47 MHz oscillator (X4) to configure the FPGA in less than 100 ms from power valid asrequired by the PCI Express Card Electromechanical Specification. This allows the PCIeinterface to be recognized and enumerated when plugged into a host PC.To achieve the fastest configuration speed, the FPGA mode pins are set to Slave SelectMAPand the onboard 47 MHz clock source external to the FPGA is used for configuration.Configuration DIP switch S2, switch 1, controls the 47 MHz oscillator enable as outlined in18. Switches.See S2 switch setting details in Table 1-26. Also, see the FPGA Design Considerations forthe Configuration Flash for FPGA design recommendations.4. 32 MB Linear BPI FlashA Numonyx JS28F256P30 Linear BPI Flash memory (P30) on the ML605 provides 32 MB ofnon-volatile storage that can be used for configuration as well as software storage. TheLinear BPI Flash shares the dual use configuration pins in parallel with the XCF128Platform Flash XL.The P30_CS net is used to select the P30 or the XCF128. Power-on configuration is selectedby the P30_CS net which is tied to a dip switch S2 (selects pullup/pulldown) and is alsowired to an FPGA non-config pin. The dip switch allows power selection for theconfiguration device P30 or XCF128XL. The dip switch selection can be overridden by theFPGA after configuration by controlling the logic level of the P30_CS signal.See S2 switch setting details in Table 1-26. For an overview on configuring the FPGA, seeConfiguration Options.Send Feedback