Xilinx ML605 User Manual

Also see for Virtex-6 FPGA: User guide Guide Hardware setup guide User guide User guide

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Xilinx ML605 User Manual Manual pdf 36 page image

36 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation Board11. 10/100/1000 Tri-Speed Ethernet PHYThe ML605 utilizes the onboard Marvell Alaska PHY device (88E1111) for Ethernetcommunications at 10, 100, or 1000 Mb/s. The board supports MII, GMII, RGMII, andSGMII interfaces from the FPGA to the PHY (Table 1-11). The PHY connection to a user-provided Ethernet cable is through a Halo HFJ11-1G01E RJ-45 connector with built-inmagnetics.On power-up, or on reset, the PHY is configured to operate in GMII mode with PHYaddress 0b00111 using the settings shown in Table 1-12. These settings can be overwrittenvia software commands passed over the MDIO interface.Table 1-10: SFP Module ConnectionsU1 FPGA Pin Schematic Net Name P4 SFP Module ConnectorPin Number Pin NameE3 SFP_RX_P 13 RDP_13E4 SFP_RX_N 12 RDN_12C3 SFP_TX_P 18 TDP_18C4 SFP_TX_N 19 TDN_19V23 SFP_LOS 8 LOSAP12 SFP_TX_DISABLE (1) 3 TX_DISABLENotes:1. The SFP TX Disable pin 3 is driven by transistor Q22, the base of which is drivenby the FPGA signal SFP_TX_DISABLE_FPGA.Table 1-11: PHY Default Interface ModeMode Jumper SettingsJ66 J67 J68GMII/MII to copper(default) Jumper over pins 1-2 Jumper over pins 1-2 No jumperSGMII to copper,no clock Jumper over pins 2-3 Jumper over pins 2-3 No jumperRGMII Jumper over pins 1-2 No jumper Jumper onTable 1-12: Board Connections for PHY Configuration PinsPin Connection onBoardBit[2]Definition and ValueBit[1]Definition and ValueBit[0]Definition and ValueCFG0 VCC 2.5V PHYADR[2] = 1 PHYADR[1] = 1 PHYADR[0] = 1CFG1 Ground ENA_PAUSE = 0 PHYADR[4] = 0 PHYADR[3] = 0CFG2 VCC 2.5V ANEG[3] = 1 ANEG[2] = 1 ANEG[1] = 1CFG3 VCC 2.5V ANEG[0] = 1 ENA_XC = 1 DIS_125 = 1CFG4 VCC 2.5V HWCFG_MD[2] = 1 HWCFG_MD[1] = 1 HWCFG_MD[0] = 1