Xilinx ML605 User Manual
Also see for Virtex-6 FPGA: User guideGuideHardware setup guideUser guideUser guide
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56 www.xilinx.com ML605 Hardware User GuideUG534 (v1.2.1) January 21, 2010Chapter 1: ML605 Evaluation BoardMode, Osc Enable, Boot EEPROM Select, and Addr Select DIP Switch S2DIP switch S2 is a multi-purpose selector switch (Figure 1-27 and Table 1-27, page 57).FPGA Mode: S2 switches 3, 4, and 5 control the FPGA mode (Table 1-26).Oscillator Enable: S2 switch 1, CCLK_EXTERNAL, controls the enable pin of the 47 MHzoscillator SiT8102 (X4). When switch 1 is closed (CCLK_EXTERNAL High), X4 drives a47 MHz clock onto the FPGA_CCLK signal.Boot EEPROM Select: S2 switch 2 is used to select the between the Xilinx Platform Flash orthe Numonyx Linear BPI Flash for the FPGA boot memory device.Upper or Lower Address Select: S2 switch 6 is used to select the upper or lower half offlash memory U4 as the source of the FPGA bitstream image. When FLASH_A23 is High,the upper half of the address is selected. When FLASH_A23 is Low, the lower half of theaddress is selected.Table 1-26 shows the FPGA configuration modes controlled by S2 switches 3, 4, and 5.X-Ref Target - Figure 1-27Figure 1-27: Multi-Purpose Select DIP Switch S2Table 1-26: ML605 Configuration ModesConfiguration Mode M[2:0] Bus Width CCLKMaster BPI-Up 010 8, 16 OutputJTAG 101 1 Input (TCK)Slave SelectMAP 110 8, 16, 32 InputUG534_27_110409SDMX-6-X4561 2 3 4 5 6987123121110S2ONVCC2V5125%1/16W510R571/16W5%125%1/16W510R5221R515101/16W5%CCLK EXTERNALP30_CS_SELFPGA_M0FPGA_M1FPGA_M2FLASH_A231212121212121/16w5%1/16w5%1/16w5%1/16w5%1/16w5%1/16w5%R43R50R53R54R55R564.7K4.7K4.7K4.7K4.7K4.7K |
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