Xilinx PCI32 Specifications

Contents

Xilinx PCI32 Specifications Manual pdf 4 page image

PCI32 Interface v3.04 www.xilinx.com DS206 August 31, 2005Product Specification v3.0.151Other FPGA resources that can be used in conjunction with the core to enable efficient implementationof a PCI system include:• Block SelectRAM™ memory. Blocks of on-chip ultra-fast RAM with synchronous write anddual-port RAM capabilities. Used in PCI designs to implement FIFOs.• SelectRAM memory. Distributed on-chip ultra-fast RAM with synchronous write option anddual-port RAM capabilities. Used in PCI designs to implement FIFOs.• Internal three-state bus capability for data multiplexing.The interface is carefully optimized for best possible performance and utilization in Xilinx FPGAdevices.Smart-IP TechnologyDrawing on the architectural advantages of Xilinx FPGAs, Xilinx Smart-IP technology ensures thehighest performance, predictability, repeatability, and flexibility in PCI designs. The Smart-IP technol-ogy is incorporated in every PCI interface.Xilinx Smart-IP technology leverages the Xilinx architectural advantages, such as look-up tables andsegmented routing, as well as floorplanning information, such as logic mapping and location con-straints. This technology provides the best physical layout, predictability, and performance. In addi-tion, these features allow for significantly reduced compile times over competing architectures.To guarantee the critical setup, hold, minimum clock-to-out, and maximum clock-to-out timing, thePCI interface is delivered with Smart-IP constraint files that are unique for a device and package com-bination. These constraint files guide the implementation tools so that the critical paths always arewithin specification.Xilinx provides Smart-IP constraint files for many device and package combinations. Constraint filesfor unsupported device and package combinations may be generated using the web-based constraintfile generator.Functional Description