Xilinx PCI32 Specifications
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PCI32 Interface v3.08 www.xilinx.com DS206 August 31, 2005Product Specification v3.0.151Timing SpecificationsThe maximum speed at which your user design is capable of running can be affected by the size andquality of the design. The following tables show the key timing parameters for the PCI Interface.Table 4 lists the Timing Parameters in the 66 MHz Implementations and Table 5 lists Timing Parametersin the 33 MHz Implementations.Table 3: PCI Bus CommandsCBE [3:0] Command PCIInitiatorPCITarget0000 Interrupt Acknowledge Yes Yes0001 Special Cycle Yes Ignore0010 I/O Read Yes Yes0011 I/O Write Yes Yes0100 Reserved Ignore Ignore0101 Reserved Ignore Ignore0110 Memory Read Yes Yes0111 Memory Write Yes Yes1000 Reserved Ignore Ignore1001 Reserved Ignore Ignore1010 Configuration Read Yes Yes1011 Configuration Write Yes Yes1100 Memory Read Multiple Yes Yes1101 Dual Address Cycle No Ignore1110 Memory Read Line Yes Yes1111 Memory Write Invalidate No Yes |
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