Xilinx PCI32 Specifications

Contents

Xilinx PCI32 Specifications Manual pdf 6 page image

PCI32 Interface v3.06 www.xilinx.com DS206 August 31, 2005Product Specification v3.0.151Target State MachineThis block controls the PCI interface target functions. The states implemented are a subset of thosedefined in Appendix B of the PCI Local Bus Specification. The target control logic uses one-hot encodingfor maximum performance.Interface ConfigurationThe PCI Interface can be easily configured to fit unique system requirements using the Xilinx COREGenerator GUI or by changing the HDL configuration file. The following customization options,among many others, are supported by the interface and are described in the PCI User Guide.• Device and vendor ID• Base Address Registers (number, size, and type)Burst TransferThe PCI bus derives its performance from its ability to support burst transfers. The performance of anyPCI application depends largely on the size of the burst transfer. Buffers to support PCI burst transfercan efficiently be implemented using on-chip RAM resources.Supported PCI CommandsTable 3 illustrates the PCI bus commands supported by the PCI Interface.Table 2: PCI Configuration Space Header31 16 15 0Device ID Vendor ID 00hStatus Command 04hClass Code Rev ID 08hBIST HeaderTypeLatencyTimerCache LineSize0ChBase Address Register 0 (BAR0) 10hBase Address Register 1 (BAR1) 14hBase Address Register 2 (BAR2) 18hBase Address Register 3 (BAR3) 1ChBase Address Register 4 (BAR4) 20hBase Address Register 5 (BAR5) 24hCardbus CIS Pointer 28hSubsystem ID Subsystem Vendor ID 2ChExpansion ROM Base Address 30hReserved CapPtr 34hReserved 38hMax Lat Min Gnt Int Pin Int Line 3ChReserved 40h-FFhNote: Shaded areas are not implemented and return zero.