Xilinx SP701 User Manual

Also see for SP701: Software Install and Board Setup

Contents

Appendix BXilinx Design ConstraintsOverviewThe Xilinx design constraints (XDC) file template for the SP701 board provides for designstargeting the SP701 evaluation board. Net names in the constraints file correlate with net nameson the latest SP701 evaluation board schematic. Identify the appropriate pins and replace the netnames with net names in the user RTL. See the Vivado Design Suite User Guide: Using Constraints(UG903) for more information.The FMC LPC connector J21 is connected to FPGA banks powered by the variable voltage VADJ(1.8V nominal). Because different FMC cards implement different circuitry, the FMC bank I/Ostandards must be uniquely defined by each customer.IMPORTANT! See the SP701 board website documentation tab (Board Files check box) for the XDC file.UG1319 (v1.0) July 12, 2019 www.xilinx.comSP701 Board User Guide 45Send Feedback