Xilinx VC709 User Manual
Also see for VC709: User guideUser guideManualManualManual
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VC709 Evaluation Board www.xilinx.com 31UG887 (v1.2.1) March 11, 2014Feature DescriptionsOne possible I/O standard for the FPGA design clock input is:NET "sysclk_233_p" LOC = "AY18" | IOSTANDARD = DIFF_SSTL15_DCI | #Bank32 MRCC inputNET "sysclk_233_n" LOC = "AY17" | IOSTANDARD = DIFF_SSTL15_DCI | #Diff.Rterm R43 DNP3. For more details, see the Si Time SiT9122 data sheet. The system clock circuit is shownin Figure 1-12.FPGA EMCC ClockNote: There is no Figure 1-2 callout for this clock.The VC709 board has a LVCMOS 80 MHz oscillator (U40) soldered onto the board andwired to the FPGA EMCCLK clock input pin AP37 on bank 14. This 80 MHz single-endedsignal is named FPGA_EMCCLK.• Oscillator: Si Time SIT8103AC-23-18E-80.0000Y• PPM frequency jitter: 50 ppm• Single-ended 1.8V LVCMOS outputThe FPGA EMCC external configuration clock circuit is shown in Figure 1-13.X-Ref Target - Figure 1-12Figure 1-12: Memory Clock SourceUG887_c1_12_011013 |
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