Xilinx ZCU106 User Manual

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Xilinx ZCU106 User Manual Manual pdf 76 page image

ZCU106 Board User Guide 76UG1244 (v1.0) March 28, 2018 www.xilinx.comChapter 3: Board Component DescriptionsHDMI Clock Recovery[Figure 2-1, callout 41]The ZCU106 board includes a Silicon Labs Si5319C jitter attenuator U108 (2 kHz – 945 MHz).The FPGA can output the RX recovered clock to a differential I/O pair on I/O bank 67(HDMI_REC_CLOCK_C_P, pin G14 and HDMI_REC_CLOCK_C_N, pin F13) for jitter attenuation.The jitter attenuated clock (HDMI_SI5324_OUT_C_P (U108 pin 28), HDMI_SI5324_OUT_C_N(U108 pin 29) is then routed as a series capacitor coupled reference clock to GTH Quad 223inputs MGTREFCLK0P (U1 pin AD8) and MGTREFCLK0N (U1 pin AD7).The Si5319C jitter attenuator is used to generate the reference clock for the HDMItransmitter subsystem. When the HDMI transmitter is used in standalone mode, theSi5319C operates in free-running mode and uses an external oscillator as the reference.When the HDMI transmitter is used in pass-through mode, the Si5319C generates ajitter-attenuated reference clock to drive the HDMI transmitter subsystem with aphase-aligned version of the HDMI Rx subsystem HMDI Rx TMDS clock, so that they arephase aligned. The SI5319C clock and jitter enable functions are controlled by HDMI IP.Communication with the SI5319C is available over the HDMI_CTL_SDA/SCL bus connectedto the XCZU7EV MPSoC U1 PL bank 87. The jitter attenuated clock circuit is shown inFigure 3-26.IMPORTANT: The Silicon Labs Si5319C U108 pin 1 reset net HDMI_SI5324_RST must be driven High toenable the device. U108 pin 1 net HDMI_SI5324_RST is connected to FPGA U1 bank 87 pin H8.X-Ref Target - Figure 3-26Figure 3-26: HDMI Interface Clock RecoveryX19190-050117Send Feedback