Xilinx virtex-5 fpga User Manual
Also see for Virtex-5 FPGA ML561: User guideUser guideUser guideUser guideUser guide
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Virtex-5 FPGA GTP Transceiver SIS Kit (IBIS-AMI) www.xilinx.com 25UG587 (v1.1) June 21, 2012Receiver CorrelationX-Ref Target - Figure A-15Figure A-15: Ideal Voltage Source, 4 Input Voltage Swings, Bias Mode = 0, ReceiveEqualization = 4, TTX-Ref Target - Figure A-16Figure A-16: Ideal Voltage Source, 4 Input Voltage Swings, Bias Mode = 0, ReceiveEqualization = 0, FFUG587_aA_15_02181018.0 19.0 20.0 21.017.016.015.0Time (ns)Volts (mV)Red = QCD Blue = HSPICE100.0-100.0-200.0-300.0-400.00.0200.0300.0400.0UG587_aA_16_02181017.0 17.50 18.0 18.50 19.016.5016.015.50Time (ns)Volts (mV)Red = QCD Blue = HSPICE100.0-100.0-200.00.0200.0300.0400.0 |
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