u-blox TOBY-L4 Series System Integration Manual

Contents

TOBY-L4 series - System Integration ManualUBX-16024839 - R04 Design-inPage 88 of 1432.6.1.2 Guidelines for USB layout designThe USB_D+/USB_D–, USB_SSTX+/USB_SSTX– and USB_SSRX+/USB_SSRX– lines require accurate layoutdesign to achieve reliable signaling at the high speed data rates (up to 480 Mbit/s or up to 5 Gbit/s) supportedby the USB 2.0 or USB 3.0 interface.The characteristic impedance of the USB_D+/USB_D–, USB_SSTX+/USB_SSTX– and USB_SSRX+/USB_SSRX–lines is specified by the USB 2.0 specification [3] and the USB 3.0 specification [4]. The most important parameteris the differential characteristic impedance applicable for the odd-mode electromagnetic field, which should beas close as possible to 90  differential. Signal integrity may be degraded if the PCB layout is not optimal,especially when the USB signaling lines are very long.Use the following general routing guidelines to minimize signal quality problems: Route USB_D+/USB_D–, USB_SSTX+/USB_SSTX– and USB_SSRX+/USB_SSRX– lines as a differential pair Route USB_D+/USB_D–, USB_SSTX+/USB_SSTX– and USB_SSRX+/USB_SSRX– lines as short as possible Ensure the differential characteristic impedance (Z0) is as close as possible to 90  Ensure the common mode characteristic impedance (ZCM) is as close as possible to 30  Consider design rules for USB_D+/USB_D–, USB_SSTX+/USB_SSTX– and USB_SSRX+/USB_SSRX– similarto RF transmission lines, these being coupled differential micro-strip or buried stripline: avoid any stubs,abrupt change of layout, and route on clear PCB areaFigure 44 and Figure 45 provide two examples of coplanar waveguide designs with differential characteristicimpedance close to 90  and common mode characteristic impedance close to 30 . The first transmission linecan be implemented for a 4-layer PCB stack-up herein illustrated; the second transmission line can beimplemented for a 2-layer PCB stack-up herein illustrated.35 μm35 μm35 μm35 μm270 μm270 μm760 μmL1 CopperL3 CopperL2 CopperL4 CopperFR-4 dielectricFR-4 dielectricFR-4 dielectric350 μm 400 μm400 μm350 μm400 μmFigure 44: Example of USB line design, with Z0 close to 90  and ZCM close to 30 , for the described 4-layer board layup35 μm35 μm1510 μmL2 CopperL1 CopperFR-4 dielectric740 μm 410 μm410 μm740 μm410 μmFigure 45: Example of USB line design, with Z0 close to 90  and ZCM close to 30 , for the described 2-layer board layup